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[PULL,13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V

Message ID 20220907080353.111926-14-alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series [PULL,01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() | expand

Commit Message

Alistair Francis Sept. 7, 2022, 8:03 a.m. UTC 
From: Alexey Baturo <baturo.alexey@gmail.com>

Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN")
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220717101543.478533-2-space.monkey.delivers@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6eeb728462..76da8db8a7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -544,7 +544,7 @@  static TCGv get_address(DisasContext *ctx, int rs1, int imm)
 
     tcg_gen_addi_tl(addr, src1, imm);
     if (ctx->pm_mask_enabled) {
-        tcg_gen_and_tl(addr, addr, pm_mask);
+        tcg_gen_andc_tl(addr, addr, pm_mask);
     } else if (get_xl(ctx) == MXL_RV32) {
         tcg_gen_ext32u_tl(addr, addr);
     }