From patchwork Wed Sep 7 08:03:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 12968604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32A9AECAAD3 for ; Wed, 7 Sep 2022 08:21:36 +0000 (UTC) Received: from localhost ([::1]:40322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVqJT-00070N-1v for qemu-devel@archiver.kernel.org; Wed, 07 Sep 2022 04:21:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVq4T-0004pm-5j for qemu-devel@nongnu.org; Wed, 07 Sep 2022 04:06:06 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:1896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVq4E-0004Ol-0p for qemu-devel@nongnu.org; Wed, 07 Sep 2022 04:06:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1662537948; x=1694073948; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7wBtZ9uUHaZW1mUfKsu18J8PFMSCFIZ4vxJKCQ83vDw=; b=BvCyv9UJwHZnBOW/65+Ujod+t7sPbftwFJerTTWTdVQWvkbornDu/BYY QK935WHKcDpNbwdbKsq8cCXND2fYDZ1QUAZLWP0B8XGQq0atd0O6f4ngC g1Cwpl9Zn//D7Ja9Zt/apBtbd+zbK/niV70hL0mY6scAb2oy7Cplnnxjf pen5fL8W2gDyLqimvmQAdlgzQgd6AQSXbvzc8HaOJXQLDsdTpvdWkmgqC AxagsPr/ivgB4Jq0+dESRs3RJlg+17bDPTI9+8PdxpvvxBEZpuID8+iJ3 3rK3aZ23ufC7ye7cuwpfhYSS8qsjSgjv/HoQ2cJ9tNdcgz/p/Dheg0kGU A==; X-IronPort-AV: E=Sophos;i="5.93,296,1654531200"; d="scan'208";a="210715047" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Sep 2022 16:04:59 +0800 IronPort-SDR: YxB7udpOZhqgeZI7omVF381lUIX9kRGjMLeOkO6pUdlXEzA6Qu9c7uJT/BMssvrFn9jHlxvGOt MwMmo3mzW7mBlgYrDD7NKdtYeyeFSCoLm2au+z7TN3PT3h+evd06E67SIMnZFtcrEvGXGaJMix 7Q2awIKF40XmCfaDEwCcfJTXszQes/VXBr6OO+aiuZqOA2tGW38oehFV2Fv8AnukpptpEVUsV+ 1pSkP6mJfeT37CarzolOXAgppHsMz3aB/9GRrD5ffzAEaKUD8A/x55j6XRL9kmQqjdyHBWK4V9 FWaLqUDZ2+/ZeNmVAxN5/sWn Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 Sep 2022 00:19:58 -0700 IronPort-SDR: MW2con3hpelCrrZHOJdYmUVVqzptt1ltAU1u7gTAMmcG47/PD3Ka0mutJEwRvM/XG5RkrUs7X1 YUo+RRxQ9yclgDCoYxjdxd2tG8dlySsH/ue+/QhNwuJZjOu9cruDYCLo/HoC1YABs5dtL1+GG4 RASeA8qHkw3U8NKx55WFbRTDCiY/4/fxsXZsu/dWYpIr5CP+9d4q4h12fex/tMawxch4zOsGQ5 6NBrGJd9Re76R7rd5ydpeTZ2UFMwG/o/M1KFM6mUdDMF3Qi/q7F+NfMSv8CWRli1B/beh4MHUY l0c= WDCIronportException: Internal Received: from unknown (HELO toolbox.wdc.com) ([10.225.167.94]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Sep 2022 01:05:00 -0700 To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Dao Lu , Heiko Stuebner , Alistair Francis Subject: [PULL 25/44] target/riscv: Add Zihintpause support Date: Wed, 7 Sep 2022 10:03:34 +0200 Message-Id: <20220907080353.111926-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907080353.111926-1-alistair.francis@wdc.com> References: <20220907080353.111926-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=242877ce7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis X-Patchwork-Original-From: Alistair Francis via From: Alistair Francis From: Dao Lu Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner Reviewed-by: Alistair Francis Signed-off-by: Dao Lu Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++++++- target/riscv/cpu.c | 2 ++ target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 561d7fa92c..4be4b82a83 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,6 +426,7 @@ struct RISCVCPUConfig { bool ext_zkt; bool ext_ifencei; bool ext_icsr; + bool ext_zihintpause; bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4033565393..595fdcdad8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r sra 0100000 ..... ..... 101 ..... 0110011 @r or 0000000 ..... ..... 110 ..... 0110011 @r and 0000000 ..... ..... 111 ..... 0110011 @r -fence ---- pred:4 succ:4 ----- 000 ----- 0001111 + +{ + pause 0000 0001 0000 00000 000 00000 0001111 + fence ---- pred:4 succ:4 ----- 000 ----- 0001111 +} + fence_i ---- ---- ---- ----- 001 ----- 0001111 csrrw ............ ..... 001 ..... 1110011 @csr csrrs ............ ..... 010 ..... 1110011 @csr diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 966e5f2dd7..d4635c7df4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -73,6 +73,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), @@ -987,6 +988,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index ca8e3d1ea1..c49dbec0eb 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -792,6 +792,22 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a) return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL); } +static bool trans_pause(DisasContext *ctx, arg_pause *a) +{ + if (!ctx->cfg_ptr->ext_zihintpause) { + return false; + } + + /* + * PAUSE is a no-op in QEMU, + * end the TB and return to main loop + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; + + return true; +} static bool trans_fence(DisasContext *ctx, arg_fence *a) {