From patchwork Tue Sep 13 10:50:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Caggiano X-Patchwork-Id: 12974696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53CDBC6FA82 for ; Tue, 13 Sep 2022 10:59:10 +0000 (UTC) Received: from localhost ([::1]:59322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oY3dF-0005AG-AI for qemu-devel@archiver.kernel.org; Tue, 13 Sep 2022 06:59:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oY3V5-0006HU-15 for qemu-devel@nongnu.org; Tue, 13 Sep 2022 06:50:43 -0400 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]:53214) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oY3Uv-00019S-BV for qemu-devel@nongnu.org; Tue, 13 Sep 2022 06:50:42 -0400 Received: from dellino.fritz.box (host-79-51-37-159.retail.telecomitalia.it [79.51.37.159]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: fahien) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7E2DA660201E; Tue, 13 Sep 2022 11:50:29 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1663066229; bh=lWh9WyS/F7ucYZTr2NF8e4IrmOwvvuFhoG0/A01n8rU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XyFNnIAcH7UAVj8+QIJ85Q+VUSDFfeZBjYor0l0GN4w5dSZEhlZxXoXW7GTlePIzC TpgJoaomJRgHLtumo0/mKO5QFN/dr/u0JXnHP0//rc5C+9OQ9Atqu+WJZzpgtQFo40 2xZuRcWOoe2EktmrKP6/7U4cqDTxslho9LrXzIgRq8z5yTzlTnvY/FMhB7g52BeShg m10USJn9fv7zZmyb28DakxHiiuZhY/t59dlVeBz4xxVxjUj5yHFTRpJYTVyNfkqNOo YwTZjnExcJMNbT6sz5zlgRxZH0f+DG7o2TJahgKGhRoDkKBuuiN1r4XtwHkyMGEf9a vTag24izGb86g== From: Antonio Caggiano To: qemu-devel@nongnu.org Cc: gert.wollny@collabora.com, dmitry.osipenko@collabora.com, "Dr. David Alan Gilbert" , "Michael S. Tsirkin" Subject: [PATCH v2 1/4] virtio: Add shared memory capability Date: Tue, 13 Sep 2022 12:50:19 +0200 Message-Id: <20220913105022.81953-2-antonio.caggiano@collabora.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913105022.81953-1-antonio.caggiano@collabora.com> References: <20220913105022.81953-1-antonio.caggiano@collabora.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1098:0:82:1000:25:2eeb:e5ab; envelope-from=antonio.caggiano@collabora.com; helo=madras.collabora.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Dr. David Alan Gilbert" Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' and the data structure 'virtio_pci_shm_cap' to go with it. They allow defining shared memory regions with sizes and offsets of 2^32 and more. Multiple instances of the capability are allowed and distinguished by a device-specific 'id'. v2: Remove virtio_pci_shm_cap as virtio_pci_cap64 is used instead. v3: No need for mask32 as cpu_to_le32 truncates the value. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Antonio Caggiano --- hw/virtio/virtio-pci.c | 18 ++++++++++++++++++ include/hw/virtio/virtio-pci.h | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a50c5a57d7..377bb06fec 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1169,6 +1169,24 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy, return offset; } +int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy, + uint8_t bar, uint64_t offset, uint64_t length, + uint8_t id) +{ + struct virtio_pci_cap64 cap = { + .cap.cap_len = sizeof cap, + .cap.cfg_type = VIRTIO_PCI_CAP_SHARED_MEMORY_CFG, + }; + + cap.cap.bar = bar; + cap.cap.length = cpu_to_le32(length); + cap.length_hi = cpu_to_le32(length >> 32); + cap.cap.offset = cpu_to_le32(offset); + cap.offset_hi = cpu_to_le32(offset >> 32); + cap.cap.id = id; + return virtio_pci_add_mem_cap(proxy, &cap.cap); +} + static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr, unsigned size) { diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 2446dcd9ae..5e5c4a4c6d 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -252,4 +252,8 @@ void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t); */ unsigned virtio_pci_optimal_num_queues(unsigned fixed_queues); +int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy, + uint8_t bar, uint64_t offset, uint64_t length, + uint8_t id); + #endif