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14 Sep 2022 02:26:23 -0700 IronPort-SDR: h0opXXfn9C7XbAKlc25dtdKEkmSiBDSjRmIyd+D0pY0yG1aRvDz7cQyfAOtEkGgHBBmptSTYEJ UkjIISqpG+wQyDfIONWdNTP0twhKo1frd5koYURAZTUUYWfLND4pqAW+rwGfWV9nmZhpUaY0IO Wf/bmcZQyYgGv7502zCb4MFmbQ6SR0MhquG4gNsVMYiual/Wp6lt2vRDPwhzxMxi0/zalmEVoE 6Lc5DKEGZmK5X74HJu8CnTMJmawIswdjFnVCTa3abToIPoPmudsJ1fUxKgUbOAtmo5egDGMuuc KCA= WDCIronportException: Internal Received: from unknown (HELO toolbox.wdc.com) ([10.225.167.107]) by uls-op-cesaip02.wdc.com with ESMTP; 14 Sep 2022 03:11:36 -0700 To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , bmeng.cn@gmail.com, Alistair Francis , alistair23@gmail.com Subject: [PATCH 2/3] hw/riscv: opentitan: Fixup resetvec Date: Wed, 14 Sep 2022 12:11:07 +0200 Message-Id: <20220914101108.82571-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220914101108.82571-1-alistair.francis@wdc.com> References: <20220914101108.82571-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=2494fb295=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alistair Francis X-Patchwork-Original-From: Alistair Francis via From: Alistair Francis The resetvec for the OpenTitan machine ended up being set to an out of date value, so let's fix that and bump it to the correct start address (after the boot ROM) Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version" Signed-off-by: Alistair Francis --- hw/riscv/opentitan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index af13dbe3b1..45c92c9bbc 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490, + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);