From patchwork Mon Sep 26 14:24:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Antonio Caggiano X-Patchwork-Id: 12988777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24A37C6FA83 for ; Mon, 26 Sep 2022 14:38:57 +0000 (UTC) Received: from localhost ([::1]:43536 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocpG4-0004YJ-3d for qemu-devel@archiver.kernel.org; Mon, 26 Sep 2022 10:38:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocp2C-0003jN-NZ for qemu-devel@nongnu.org; Mon, 26 Sep 2022 10:24:36 -0400 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]:33126) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocp2A-00043X-Ox for qemu-devel@nongnu.org; Mon, 26 Sep 2022 10:24:36 -0400 Received: from dellino.fritz.box (host-79-27-165-192.retail.telecomitalia.it [79.27.165.192]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: fahien) by madras.collabora.co.uk (Postfix) with ESMTPSA id 40EF76602258; Mon, 26 Sep 2022 15:24:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1664202271; bh=DOVlmH6R/glWZov62i99PaXzdBdIGZEN0epjvHBVYXw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G4/XYu1FUbqLYB7b342IsM/Xdn0fmGnpz/BDYVXmtO3FDnSZWYUS+Jo6Y4MhIZ2HQ VEV296feEFqT52hqyP9tCLkXiymEMYWkGXjQIl5aqVNVdUTZXBpL/aKMsWkMTjV8cN 5mUqCc5aZIMPA4b/YVXPgjYwUUzTpIVrDv+snyyS6uePjTTtRxC3QSNrLHYgn0kzPV v/gyMrjKHUR1bWI0MMvN1bSai+DD4O7G3lFTEfCv+IVGVcI9cdtMwRyVneRTbt2goe Ve7wNbh7beBwfHUvHIeZ0+hxgwLqUuPwgXoot040d2qfT8odkY4JiK5Pnp/1wOvFqf zUhDCss8WLcrg== From: Antonio Caggiano To: qemu-devel@nongnu.org Cc: gert.wollny@collabora.com, dmitry.osipenko@collabora.com, "Dr. David Alan Gilbert" , "Michael S. Tsirkin" Subject: [PATCH v3 1/9] virtio: Add shared memory capability Date: Mon, 26 Sep 2022 16:24:14 +0200 Message-Id: <20220926142422.22325-2-antonio.caggiano@collabora.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926142422.22325-1-antonio.caggiano@collabora.com> References: <20220926142422.22325-1-antonio.caggiano@collabora.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1098:0:82:1000:25:2eeb:e5ab; envelope-from=antonio.caggiano@collabora.com; helo=madras.collabora.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Dr. David Alan Gilbert" Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' to allow defining shared memory regions with sizes and offsets of 2^32 and more. Multiple instances of the capability are allowed and distinguished by a device-specific 'id'. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Antonio Caggiano Reviewed-by: Alex Bennée --- v3: - Remove virtio_pci_shm_cap as virtio_pci_cap64 is used instead. - No need for mask32 as cpu_to_le32 truncates the value. hw/virtio/virtio-pci.c | 18 ++++++++++++++++++ include/hw/virtio/virtio-pci.h | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a50c5a57d7..377bb06fec 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1169,6 +1169,24 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy, return offset; } +int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy, + uint8_t bar, uint64_t offset, uint64_t length, + uint8_t id) +{ + struct virtio_pci_cap64 cap = { + .cap.cap_len = sizeof cap, + .cap.cfg_type = VIRTIO_PCI_CAP_SHARED_MEMORY_CFG, + }; + + cap.cap.bar = bar; + cap.cap.length = cpu_to_le32(length); + cap.length_hi = cpu_to_le32(length >> 32); + cap.cap.offset = cpu_to_le32(offset); + cap.offset_hi = cpu_to_le32(offset >> 32); + cap.cap.id = id; + return virtio_pci_add_mem_cap(proxy, &cap.cap); +} + static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr, unsigned size) { diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 2446dcd9ae..5e5c4a4c6d 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -252,4 +252,8 @@ void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t); */ unsigned virtio_pci_optimal_num_queues(unsigned fixed_queues); +int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy, + uint8_t bar, uint64_t offset, uint64_t length, + uint8_t id); + #endif