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[PULL,00/20] tcg patch queue

Message ID 20221004195241.46491-1-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show

Pull-request

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221004

Message

Richard Henderson Oct. 4, 2022, 7:52 p.m. UTC 
TCG patch queue, plus one target/sh4 patch that
Yoshinori Sato asked me to process.


r~


The following changes since commit efbf38d73e5dcc4d5f8b98c6e7a12be1f3b91745:

  Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging (2022-10-03 15:06:07 -0400)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221004

for you to fetch changes up to ab419fd8a035a65942de4e63effcd55ccbf1a9fe:

  target/sh4: Fix TB_FLAG_UNALIGN (2022-10-04 12:33:05 -0700)

----------------------------------------------------------------
Cache CPUClass for use in hot code paths.
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
Add generic support for TARGET_TB_PCREL.
tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
target/sh4: Fix TB_FLAG_UNALIGN

----------------------------------------------------------------
Alex Bennée (3):
      cpu: cache CPUClass in CPUState for hot code paths
      hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
      cputlb: used cached CPUClass in our hot-paths

Leandro Lupori (1):
      tcg/ppc: Optimize 26-bit jumps

Richard Henderson (16):
      accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
      accel/tcg: Drop addr member from SavedIOTLB
      accel/tcg: Suppress auto-invalidate in probe_access_internal
      accel/tcg: Introduce probe_access_full
      accel/tcg: Introduce tlb_set_page_full
      include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
      accel/tcg: Remove PageDesc code_bitmap
      accel/tcg: Use bool for page_find_alloc
      accel/tcg: Use DisasContextBase in plugin_gen_tb_start
      accel/tcg: Do not align tb->page_addr[0]
      accel/tcg: Inline tb_flush_jmp_cache
      include/hw/core: Create struct CPUJumpCache
      hw/core: Add CPUClass.get_pc
      accel/tcg: Introduce tb_pc and log_pc
      accel/tcg: Introduce TARGET_TB_PCREL
      target/sh4: Fix TB_FLAG_UNALIGN

 accel/tcg/internal.h                    |  10 ++
 accel/tcg/tb-hash.h                     |   1 +
 accel/tcg/tb-jmp-cache.h                |  65 ++++++++
 include/exec/cpu-common.h               |   1 +
 include/exec/cpu-defs.h                 |  48 ++++--
 include/exec/exec-all.h                 |  75 ++++++++-
 include/exec/plugin-gen.h               |   7 +-
 include/hw/core/cpu.h                   |  28 ++--
 include/qemu/typedefs.h                 |   2 +
 include/tcg/tcg.h                       |   2 +-
 target/sh4/cpu.h                        |  56 ++++---
 accel/stubs/tcg-stub.c                  |   4 +
 accel/tcg/cpu-exec.c                    |  80 +++++-----
 accel/tcg/cputlb.c                      | 259 ++++++++++++++++++--------------
 accel/tcg/plugin-gen.c                  |  22 +--
 accel/tcg/translate-all.c               | 214 ++++++++++++--------------
 accel/tcg/translator.c                  |   2 +-
 cpu.c                                   |   9 +-
 hw/core/cpu-common.c                    |   3 +-
 hw/core/cpu-sysemu.c                    |   5 +-
 linux-user/sh4/signal.c                 |   6 +-
 plugins/core.c                          |   2 +-
 target/alpha/cpu.c                      |   9 ++
 target/arm/cpu.c                        |  17 ++-
 target/arm/mte_helper.c                 |  14 +-
 target/arm/sve_helper.c                 |   4 +-
 target/arm/translate-a64.c              |   2 +-
 target/avr/cpu.c                        |  10 +-
 target/cris/cpu.c                       |   8 +
 target/hexagon/cpu.c                    |  10 +-
 target/hppa/cpu.c                       |  12 +-
 target/i386/cpu.c                       |   9 ++
 target/i386/tcg/tcg-cpu.c               |   2 +-
 target/loongarch/cpu.c                  |  11 +-
 target/m68k/cpu.c                       |   8 +
 target/microblaze/cpu.c                 |  10 +-
 target/mips/cpu.c                       |   8 +
 target/mips/tcg/exception.c             |   2 +-
 target/mips/tcg/sysemu/special_helper.c |   2 +-
 target/nios2/cpu.c                      |   9 ++
 target/openrisc/cpu.c                   |  10 +-
 target/ppc/cpu_init.c                   |   8 +
 target/riscv/cpu.c                      |  17 ++-
 target/rx/cpu.c                         |  10 +-
 target/s390x/cpu.c                      |   8 +
 target/s390x/tcg/mem_helper.c           |   4 -
 target/sh4/cpu.c                        |  18 ++-
 target/sh4/helper.c                     |   6 +-
 target/sh4/translate.c                  |  90 +++++------
 target/sparc/cpu.c                      |  10 +-
 target/tricore/cpu.c                    |  11 +-
 target/xtensa/cpu.c                     |   8 +
 tcg/tcg.c                               |   8 +-
 trace/control-target.c                  |   2 +-
 tcg/ppc/tcg-target.c.inc                | 119 +++++++++++----
 55 files changed, 915 insertions(+), 462 deletions(-)
 create mode 100644 accel/tcg/tb-jmp-cache.h

Comments

Stefan Hajnoczi Oct. 5, 2022, 5:55 p.m. UTC | #1 
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.