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[109.184.32.144]) by smtp.gmail.com with ESMTPSA id p8-20020a2eb988000000b0026dd2038b99sm2437072ljp.132.2022.10.19.05.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 05:15:40 -0700 (PDT) From: Timofey Kutergin To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Timofey Kutergin Subject: [PATCH] target/arm: Fixed Privileged Access Never (PAN) for aarch32 Date: Wed, 19 Oct 2022 15:15:37 +0300 Message-Id: <20221019121537.255477-1-tkutergin@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=tkutergin@gmail.com; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 19 Oct 2022 09:18:21 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" - synchronize PSTATE.PAN with changes in CPSR.PAN in aarch32 mode - set PAN bit automatically on exception entry if SCTLR_SPAN bit is set - throw permission fault during address translation when PAN is enabled and kernel tries to access user acessible page - ignore SCTLR_XP bit for armv7 and armv8 (conflicts with SCTLR_SPAN). Signed-off-by: Timofey Kutergin --- target/arm/helper.c | 6 ++++++ target/arm/ptw.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dde64a487a..5299f67e3f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9052,6 +9052,11 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, } mask &= ~CACHED_CPSR_BITS; env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); + if (env->uncached_cpsr & CPSR_PAN) { + env->pstate |= PSTATE_PAN; + } else { + env->pstate &= ~PSTATE_PAN; + } if (rebuild_hflags) { arm_rebuild_hflags(env); } @@ -9592,6 +9597,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, /* ... the target is EL1 and SCTLR.SPAN is 0. */ if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { env->uncached_cpsr |= CPSR_PAN; + env->pstate |= PSTATE_PAN; } break; } diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 23f16f4ff7..204a73350f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -659,6 +659,13 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, goto do_fault; } + if (regime_is_pan(env, mmu_idx) && !regime_is_user(env, mmu_idx) && + simple_ap_to_rw_prot_is_user(ap >> 1, 1) && + access_type != MMU_INST_FETCH) { + fi->type = ARMFault_Permission; + goto do_fault; + } + if (arm_feature(env, ARM_FEATURE_V6K) && (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { /* The simplified model uses AP[0] as an access control bit. */ @@ -2506,7 +2513,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, is_secure, false, result, fi); - } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { + } else if (arm_feature(env, ARM_FEATURE_V7) || + arm_feature(env, ARM_FEATURE_V8) || ( + regime_sctlr(env, mmu_idx) & SCTLR_XP)) { return get_phys_addr_v6(env, address, access_type, mmu_idx, is_secure, result, fi); } else {