From patchwork Sat Oct 22 15:04:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F5BFC433FE for ; Mon, 24 Oct 2022 02:29:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omh0a-00041Z-Aw for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:51:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4u-00078G-T1; Sat, 22 Oct 2022 11:06:24 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4s-0001zz-PH; Sat, 22 Oct 2022 11:06:24 -0400 Received: by mail-ed1-x52b.google.com with SMTP id b12so16120544edd.6; Sat, 22 Oct 2022 08:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+ww6Kq9R9MXGQUZI0FRh4YiaC+URONXcXyo6Qx0sa7I=; b=edcC0RumObm9h8qTrLdCbm5XOWoXzHEZLS+LmC7mnDWdNPKWKGHS8YW/I1HREW/jf0 nn1NERO3Eb08vVS8NRyhzpMLGzFZevSsRbxBMKOPDV6oKbcNCC/6zM3HC271HbRTe6FE JpdlKZdyhl63I13+sB2gTCFGEVGiGrSTxPapF9TKi1PyIcriQ+Bd54nbSvKtXDMvtmNx KQCLsklq3X0GvxtPKY+vH8mFGwZI9Sys0I5xpzoPkvls6fcUHUZ8swfZmgfAaMTDw+7Y XaZm0TEmB06O70/nAbmDOmFFCTb1KDSzd/fCao4/fIOVMK/VSTP/jvshbQ29pENoCRlJ 0tfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+ww6Kq9R9MXGQUZI0FRh4YiaC+URONXcXyo6Qx0sa7I=; b=Wwi1dsOItAKQtfjuVjpXpnHTyZmczrrpiUHqIQi7rhALPuq2mdcrPN8Ideyv3ZG7Tj v9mlLwx4pq/zOHOIhG6GsHK1wr8a5xg/iqZU/BbuY49dgfiWwh9lmhaxs5kq0QYNjX7h ySWI5Z+/wlaZ/Y0CZeH2N8IAXJjgkQq0RIGXJZyunzDyopSUwt9Ihpxvrw/D8Pe8dX3Z 8bd8iz/sVY6l7R352BhSdlKVa9o3zg3QT8Cr2gBixg/pUVuBezWD4VRWiM5a40ix2ia7 yrazq4JyZm5mJD5AdX6T2z98e34ajUtOywyb1cBgIUvBG4cmWYOKF9LDyFrLjgpjHBXb YtXQ== X-Gm-Message-State: ACrzQf26Ign03cW/lqrGmTLi1h8uTk7nV0oudpJqtuaMAbw18mDlc/qy 8Zoez7HuRC62GhT3Mp9V3zsQmZb4A5jN4w== X-Google-Smtp-Source: AMsMyM6xjUwHu3eOkz7B90jUTMVAWahMSA0EmYl99regY6DV/uuu9ocGoILYpZ3twEWtoLBVlV6ETQ== X-Received: by 2002:a05:6402:5489:b0:43b:b935:db37 with SMTP id fg9-20020a056402548900b0043bb935db37mr23107088edb.347.1666451181549; Sat, 22 Oct 2022 08:06:21 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:06:19 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 12/43] hw/isa/piix3: Create USB controller in host device Date: Sat, 22 Oct 2022 17:04:37 +0200 Message-Id: <20221022150508.26830-13-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The USB controller is an integral part of PIIX3 (function 2). So create it as part of the south bridge. Note that the USB function is optional in QEMU. This is why it gets object_initialize_child()'ed in realize rather than in instance_init. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 7 ++----- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 17 +++++++++++++++++ include/hw/southbridge/piix.h | 4 ++++ 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index b97bff5674..22c1c5404c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -51,7 +51,6 @@ #include "exec/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/piix4.h" -#include "hw/usb/hcd-uhci.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -221,6 +220,8 @@ static void pc_init1(MachineState *machine, pcms->bus = pci_bus; pci_dev = pci_new_multifunction(-1, true, type); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -299,10 +300,6 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI); - } - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { PCIDevice *piix4_pm; diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 6e8f9cac54..f02eca3c3e 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -36,6 +36,7 @@ config PIIX3 select I8257 select ISA_BUS select MC146818RTC + select USB_UHCI config PIIX4 bool diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 75c6370e33..2f227fde0e 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -300,6 +300,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev), @@ -320,6 +321,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { return; } + + /* USB */ + if (d->has_usb) { + object_initialize_child(OBJECT(dev), "uhci", &d->uhci, + TYPE_PIIX3_USB_UHCI); + qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { + return; + } + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -342,6 +353,11 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); } +static Property pci_piix3_props[] = { + DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -361,6 +377,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; + device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml = build_pci_isa_aml; } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b1fa08dd2b..5367917182 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -54,12 +55,15 @@ struct PIIXState { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; RTCState rtc; + UHCIState uhci; /* Reset Control Register contents */ uint8_t rcr; /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + + bool has_usb; }; typedef struct PIIXState PIIX3State;