Message ID | 20221022150508.26830-3-shentey@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:05:50 -0700 (PDT) From: Bernhard Beschow <shentey@gmail.com> To: qemu-devel@nongnu.org Cc: Eduardo Habkost <eduardo@habkost.net>, =?utf-8?q?Herv=C3=A9_Poussineau?= <hpoussin@reactos.org>, Aurelien Jarno <aurelien@aurel32.net>, Igor Mammedov <imammedo@redhat.com>, Gerd Hoffmann <kraxel@redhat.com>, John Snow <jsnow@redhat.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Ani Sinha <ani@anisinha.ca>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, qemu-block@nongnu.org, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= <f4bug@amsat.org>, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= <philmd@linaro.org>, "Michael S. Tsirkin" <mst@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Bernhard Beschow <shentey@gmail.com>, Peter Maydell <peter.maydell@linaro.org> Subject: [PATCH v2 02/43] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Date: Sat, 22 Oct 2022 17:04:27 +0200 Message-Id: <20221022150508.26830-3-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022150508.26830-1-shentey@gmail.com> References: <20221022150508.26830-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> |
Series |
Consolidate PIIX south bridges
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expand
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diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7a55b9ca8e..5caef9bfc9 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -217,7 +217,8 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); + pci_dev = pci_new_multifunction(-1, true, type); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn;