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[2003:fa:af0b:b200:9c49:4783:8afc:41b6]) by smtp.gmail.com with ESMTPSA id 13-20020a170906328d00b00730b3bdd8d7sm3032524ejw.179.2022.10.26.06.31.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 06:31:58 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Marcel Apfelbaum , qemu-trivial@nongnu.org, Ani Sinha , Igor Mammedov , Richard Henderson , Eduardo Habkost , Paolo Bonzini , Bernhard Beschow Subject: [PATCH 4/4] hw/i386/acpi-build: Generate AML for north and south bridges separately Date: Wed, 26 Oct 2022 15:31:10 +0200 Message-Id: <20221026133110.91828-5-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221026133110.91828-1-shentey@gmail.com> References: <20221026133110.91828-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The code currently assumes Q35 iff ICH9 and i440fx iff PIIX. This is slightly confusing when trying to understand the code. Split north and south bridge code to communicate which piece of code assumes which type of bridge. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/acpi-build.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f0a20c8b21..8fbe223d08 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -60,6 +60,7 @@ #include "hw/i386/fw_cfg.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/pci-host/i440fx.h" #include "hw/pci-host/q35.h" #include "hw/i386/x86-iommu.h" @@ -1437,6 +1438,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, Range *pci_hole, Range *pci_hole64, MachineState *machine) { + Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); + Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); Object *piix = object_resolve_type_unambiguous(TYPE_PIIX3_PCI_DEVICE); Object *ich9 = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); CrsRangeEntry *entry; @@ -1459,13 +1462,14 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, .oem_table_id = x86ms->oem_table_id }; + assert(!!i440fx != !!q35); assert(!!piix != !!ich9); acpi_table_begin(&table, table_data); dsdt = init_aml_allocator(); build_dbg_aml(dsdt); - if (piix) { + if (i440fx) { sb_scope = aml_scope("_SB"); dev = aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); @@ -1473,13 +1477,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))); aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); - - build_piix4_isa_bridge(dsdt); - if (pm->pcihp_bridge_en || pm->pcihp_root_en) { - build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); - } - build_piix4_pci0_int(dsdt); - } else if (ich9) { + } else if (q35) { sb_scope = aml_scope("_SB"); dev = aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); @@ -1518,7 +1516,15 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dsdt, sb_scope); + } + if (piix) { + build_piix4_isa_bridge(dsdt); + if (pm->pcihp_bridge_en || pm->pcihp_root_en) { + build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); + } + build_piix4_pci0_int(dsdt); + } else if (ich9) { build_q35_isa_bridge(dsdt); if (pm->pcihp_bridge_en) { build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);