| Message ID | 20221027164743.194265-4-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Nested virtualization fixes for QEMU | expand |
On Fri, Oct 28, 2022 at 2:52 AM Anup Patel <apatel@ventanamicro.com> wrote: > > Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we > should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c > for VSTIP. > > Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") > Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 2 -- > target/riscv/time_helper.c | 12 ++++++++---- > 2 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 5d66246c2c..a403825e49 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -617,8 +617,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) > vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; > } > > - /* No need to update mip for VSTIP */ > - mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; > vstip = env->vstime_irq ? MIP_VSTIP : 0; > > if (!qemu_mutex_iothread_locked()) { > diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c > index 8cce667dfd..4fb2a471a9 100644 > --- a/target/riscv/time_helper.c > +++ b/target/riscv/time_helper.c > @@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque) > RISCVCPU *cpu = opaque; > CPURISCVState *env = &cpu->env; > env->vstime_irq = 1; > - riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); > + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); > } > > static void riscv_stimer_cb(void *opaque) > @@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, > */ > if (timer_irq == MIP_VSTIP) { > env->vstime_irq = 1; > + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); > + } else { > + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); > } > - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); > return; > } > > + /* Clear the [VS|S]TIP bit in mip */ > if (timer_irq == MIP_VSTIP) { > env->vstime_irq = 0; > + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); > + } else { > + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); > } > - /* Clear the [V]STIP bit in mip */ > - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); > > /* otherwise, set up the future timer interrupt */ > diff = timecmp - rtc_r; > -- > 2.34.1 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5d66246c2c..a403825e49 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -617,8 +617,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } - /* No need to update mip for VSTIP */ - mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; vstip = env->vstime_irq ? MIP_VSTIP : 0; if (!qemu_mutex_iothread_locked()) { diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 8cce667dfd..4fb2a471a9 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque) RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; env->vstime_irq = 1; - riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); } static void riscv_stimer_cb(void *opaque) @@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 1; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + } else { + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); } - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); return; } + /* Clear the [VS|S]TIP bit in mip */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 0; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); + } else { + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } - /* Clear the [V]STIP bit in mip */ - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r;
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c for VSTIP. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- target/riscv/cpu_helper.c | 2 -- target/riscv/time_helper.c | 12 ++++++++---- 2 files changed, 8 insertions(+), 6 deletions(-)