From patchwork Sun Oct 30 22:27:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13025243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B35D2ECAAA1 for ; Sun, 30 Oct 2022 22:30:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opGnY-0008QK-UG; Sun, 30 Oct 2022 18:28:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opGnX-0008Q7-Ld for qemu-devel@nongnu.org; Sun, 30 Oct 2022 18:28:55 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opGnV-00079Q-Nm for qemu-devel@nongnu.org; Sun, 30 Oct 2022 18:28:55 -0400 Received: by mail-wr1-x432.google.com with SMTP id cl5so2012816wrb.9 for ; Sun, 30 Oct 2022 15:28:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qrrHIqKWzq8VKmzufjfxmHBNMS1dtubnUSDhMzms0L8=; b=MGnD4nqxz0j/iWyXcgAmR81421WGnIjJv/dZfDaE2f66JmkqJ+HK0uGnmC6R3P4aK7 WPJnVdZRu+Kxou3W4xrAE1xbmVhnnV1itp3vbtfy/J7NDA/tBCSak5fVRA7OwtdmO0bs V6R714ixLBPlyCuEyr7x5FuF+Iq9tnhfjlZmTPLN4lsrv5u2pvWT/ah6g1qR5evuFLSQ IjJ0Vm+waFmGCGMLEqu32DYC9Ghi0a8weKWPMOX1S8OCnMDoK4bpPdizRaC28fZ2zB6d jkhhkAy+IUMhS2tyayMyrWkrM0MOSQ3pTP8PxMPjfuxKJJLr/yJxAKzLY5lB/rxKD302 uGXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qrrHIqKWzq8VKmzufjfxmHBNMS1dtubnUSDhMzms0L8=; b=Y367W/+6vcLUUZe9tkgOuOqWirSreu9LKsa1rY/w5J+HUJIn2hLK2HgK5fXopr/O0x ECutBolNicnkShX5SRKaYOsyEgnc/foahZyZgaDzTyrplH1k4cUb1cGYA6oEbIq+S1TV 6B0cxybAwPv5qA0rEzzeIxxRbXqYaxrxfcunacHwbE4PTjx9dEJWjBHLFcaUZx2wFgyx hE+jHRLoNgK+hIHvkzxIjORRL5/SsdE1+4KFyDO0Ww8GPHk35241myGrSv/nrP1g+azf prwrbeA5G+yuv/DdFrvDQaDIrO77ReGsT2zHbSYPEIfsa+5timN8sXg2oKtGw4tdAI8/ i/5Q== X-Gm-Message-State: ACrzQf1e4Pfzef6uS/FADnv5swLkFcuKVvCBLGo631IOJcjlT+KKrYpR P+XudMnviTyLeVa72zeSLSlKXbammZddsQ== X-Google-Smtp-Source: AMsMyM7JRjZeqK6Bf4Nsdf76ZossAJz5wnkfu32D45+hZof3Sb4H+JZ0wU6lLz5CvF2mHLyylMD0Pg== X-Received: by 2002:adf:f651:0:b0:236:9cb8:b939 with SMTP id x17-20020adff651000000b002369cb8b939mr5869286wrp.546.1667168931944; Sun, 30 Oct 2022 15:28:51 -0700 (PDT) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id j7-20020a05600c190700b003b47e8a5d22sm6304977wmq.23.2022.10.30.15.28.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 30 Oct 2022 15:28:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Stefan Pejic , Jiaxun Yang , Aurelien Jarno , Paul Burton , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 01/55] hw/isa/vt82c686: Resolve chip-specific realize methods Date: Sun, 30 Oct 2022 23:27:47 +0100 Message-Id: <20221030222841.42377-2-philmd@linaro.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221030222841.42377-1-philmd@linaro.org> References: <20221030222841.42377-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bernhard Beschow The object creation now happens in chip-specific init methods which allows the realize methods to be consolidated into one method. Shifting the logic into the init methods has the addidional advantage that the parent object's init methods are called implicitly - like constructors in object-oriented languages. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220901114127.53914-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/vt82c686.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 8f656251b8..0217c98fe4 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -544,7 +544,7 @@ struct ViaISAState { qemu_irq cpu_intr; qemu_irq *isa_irqs; ISABus *isa_bus; - ViaSuperIOState *via_sio; + ViaSuperIOState via_sio; }; static const VMStateDescription vmstate_via = { @@ -602,6 +602,11 @@ static void via_isa_realize(PCIDevice *d, Error **errp) d->wmask[i] = 0; } } + + /* Super I/O */ + if (!qdev_realize(DEVICE(&s->via_sio), BUS(s->isa_bus), errp)) { + return; + } } /* TYPE_VT82C686B_ISA */ @@ -615,7 +620,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, pci_default_write_config(d, addr, val, len); if (addr == 0x85) { /* BIT(1): enable or disable superio config io ports */ - via_superio_io_enable(s->via_sio, val & BIT(1)); + via_superio_io_enable(&s->via_sio, val & BIT(1)); } } @@ -639,13 +644,11 @@ static void vt82c686b_isa_reset(DeviceState *dev) pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ } -static void vt82c686b_realize(PCIDevice *d, Error **errp) +static void vt82c686b_init(Object *obj) { - ViaISAState *s = VIA_ISA(d); + ViaISAState *s = VIA_ISA(obj); - via_isa_realize(d, errp); - s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus, - TYPE_VT82C686B_SUPERIO)); + object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT82C686B_SUPERIO); } static void vt82c686b_class_init(ObjectClass *klass, void *data) @@ -653,7 +656,7 @@ static void vt82c686b_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->realize = vt82c686b_realize; + k->realize = via_isa_realize; k->config_write = vt82c686b_write_config; k->vendor_id = PCI_VENDOR_ID_VIA; k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA; @@ -670,6 +673,7 @@ static const TypeInfo vt82c686b_isa_info = { .name = TYPE_VT82C686B_ISA, .parent = TYPE_VIA_ISA, .instance_size = sizeof(ViaISAState), + .instance_init = vt82c686b_init, .class_init = vt82c686b_class_init, }; @@ -684,7 +688,7 @@ static void vt8231_write_config(PCIDevice *d, uint32_t addr, pci_default_write_config(d, addr, val, len); if (addr == 0x50) { /* BIT(2): enable or disable superio config io ports */ - via_superio_io_enable(s->via_sio, val & BIT(2)); + via_superio_io_enable(&s->via_sio, val & BIT(2)); } } @@ -703,13 +707,11 @@ static void vt8231_isa_reset(DeviceState *dev) pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */ } -static void vt8231_realize(PCIDevice *d, Error **errp) +static void vt8231_init(Object *obj) { - ViaISAState *s = VIA_ISA(d); + ViaISAState *s = VIA_ISA(obj); - via_isa_realize(d, errp); - s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus, - TYPE_VT8231_SUPERIO)); + object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT8231_SUPERIO); } static void vt8231_class_init(ObjectClass *klass, void *data) @@ -717,7 +719,7 @@ static void vt8231_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->realize = vt8231_realize; + k->realize = via_isa_realize; k->config_write = vt8231_write_config; k->vendor_id = PCI_VENDOR_ID_VIA; k->device_id = PCI_DEVICE_ID_VIA_8231_ISA; @@ -734,6 +736,7 @@ static const TypeInfo vt8231_isa_info = { .name = TYPE_VT8231_ISA, .parent = TYPE_VIA_ISA, .instance_size = sizeof(ViaISAState), + .instance_init = vt8231_init, .class_init = vt8231_class_init, };