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[219.106.231.132]) by smtp.gmail.com with ESMTPSA id g139-20020a625291000000b0056d2797bf05sm3478385pfb.217.2022.10.31.01.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 01:46:02 -0700 (PDT) From: Ake Koomsin To: qemu-devel@nongnu.org Cc: Ake Koomsin , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2] target/arm: honor HCR_E2H and HCR_TGE in ats_write64() Date: Mon, 31 Oct 2022 17:43:25 +0900 Message-Id: <20221031084324.844220-1-ake@igel.co.jp> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=ake@igel.co.jp; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We need to check HCR_E2H and HCR_TGE to select the right MMU index for the correct translation regime. To check for EL2&0 translation regime: - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE - For S1E2* ops, check only HCR_E2H Signed-off-by: Ake Koomsin --- v2: - Rebase with the latest upstream - It turns out that we need to check both HCR_E2H and HCR_TGE for S1E0*, S1E1* and S12E* address translation as well according to the Architecture Manual. v1: https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg02627.html target/arm/helper.c | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b070a20f1a..f7b988395a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3501,19 +3501,33 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; ARMMMUIdx mmu_idx; int secure = arm_is_secure_below_el3(env); + bool regime_e20 = (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) == + (HCR_E2H | HCR_TGE); switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx = ARMMMUIdx_Stage1_E1_PAN; + if (regime_e20) { + mmu_idx = ARMMMUIdx_E20_2_PAN; + } else { + mmu_idx = ARMMMUIdx_Stage1_E1_PAN; + } } else { - mmu_idx = ARMMMUIdx_Stage1_E1; + if (regime_e20) { + mmu_idx = ARMMMUIdx_E20_2; + } else { + mmu_idx = ARMMMUIdx_Stage1_E1; + } } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx = ARMMMUIdx_E2; + if ((arm_hcr_el2_eff(env) & HCR_E2H) == HCR_E2H) { + mmu_idx = ARMMMUIdx_E20_2; + } else { + mmu_idx = ARMMMUIdx_E2; + } break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx = ARMMMUIdx_E3; @@ -3524,13 +3538,25 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx = ARMMMUIdx_Stage1_E0; + if (regime_e20) { + mmu_idx = ARMMMUIdx_E20_0; + } else { + mmu_idx = ARMMMUIdx_Stage1_E0; + } break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx = ARMMMUIdx_E10_1; + if (regime_e20) { + mmu_idx = ARMMMUIdx_E20_2; + } else { + mmu_idx = ARMMMUIdx_E10_1; + } break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx = ARMMMUIdx_E10_0; + if (regime_e20) { + mmu_idx = ARMMMUIdx_E20_0; + } else { + mmu_idx = ARMMMUIdx_E10_0; + } break; default: g_assert_not_reached();