diff mbox series

[v2,1/3] target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F

Message ID 20221031132531.18122-2-jiaxun.yang@flygoat.com (mailing list archive)
State New, archived
Headers show
Series MIPS system emulation miscellaneous fixes | expand

Commit Message

Jiaxun Yang Oct. 31, 2022, 1:25 p.m. UTC 
As per an unpublished document, in later reversion of chips
CP0St_{KX, SX, UX} is not writeable and hardcoded to 1.

Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
---
v2:
Rewording to point out the document is unpublished
---
 target/mips/cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d0a76b95f7..a870901bfa 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -304,6 +304,12 @@  static void mips_cpu_reset(DeviceState *dev)
     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
+    if (env->insn_flags & INSN_LOONGSON2F) {
+        /* Loongson-2F has those bits hardcoded to 1 */
+        env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) |
+                            (1 << CP0St_UX);
+    }
+
     /*
      * Vectored interrupts not implemented, timer on int 7,
      * no performance counters.