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Sat, 10 Dec 2022 07:55:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Milica Lazarevic , Dragan Mladjenovic , Aurelien Jarno , Djordje Todorovic , Jiaxun Yang , Bernhard Beschow Subject: [PATCH-for-8.0 6/7] hw/mips/bootloader: Implement nanoMIPS SW opcode Date: Sat, 10 Dec 2022 16:55:01 +0100 Message-Id: <20221210155502.74609-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221210155502.74609-1-philmd@linaro.org> References: <20221210155502.74609-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index cc3df385df..541b59bf84 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -177,9 +177,32 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) } } +static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t offset) +{ + uint16_t *p = (uint16_t *)*ptr; + uint32_t insn = 0; + + insn = deposit32(insn, 26, 6, 0b100001); + insn = deposit32(insn, 21, 5, rt); + insn = deposit32(insn, 16, 5, rs); + insn = deposit32(insn, 12, 4, 0b1001); + insn = deposit32(insn, 0, 12, offset); + + stw_p(p, insn >> 16); + p++; + stw_p(p, insn >> 0); + p++; + + *ptr = p; +} + static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) { - bl_gen_i_type(p, 0x2b, base, rt, offset); + if (bootcpu_supports_isa(ISA_NANOMIPS32)) { + bl_gen_sw_nm(p, rt, base, offset); + } else { + bl_gen_i_type(p, 0x2b, base, rt, offset); + } } static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)