diff mbox series

[PATCH-for-8.0,v2,10/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)

Message ID 20221211204533.85359-11-philmd@linaro.org (mailing list archive)
State New, archived
Headers show
Series hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API | expand

Commit Message

Philippe Mathieu-Daudé Dec. 11, 2022, 8:45 p.m. UTC 
Part 5/5: Convert jumping to kernel

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 68 ++++++++-----------------------------------------
 1 file changed, 11 insertions(+), 57 deletions(-)

Comments

Richard Henderson Dec. 12, 2022, 2:53 p.m. UTC | #1 
On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Part 5/5: Convert jumping to kernel
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/malta.c | 68 ++++++++-----------------------------------------
>   1 file changed, 11 insertions(+), 57 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~


> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 451908b217..876bc26a7f 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -619,11 +619,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>       /* Small bootloader */
>       p = (uint16_t *)base;
>   
> -#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
> -#define NM_HI2(VAL) \
> -          (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
> -#define NM_LO(VAL)  ((VAL) & 0xfff)
> -
>       stw_p(p++, 0x2800); stw_p(p++, 0x001c);
>                                   /* bc to_here */
>       stw_p(p++, 0x8000); stw_p(p++, 0xc000);
> @@ -642,46 +637,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>                                   /* nop */
>   
>       /* to_here: */
> -    if (semihosting_get_argc()) {
> -        /* Preserve a0 content as arguments have been passed    */
> -        stw_p(p++, 0x8000); stw_p(p++, 0xc000);
> -                                /* nop                          */
> -    } else {
> -        stw_p(p++, 0x0080); stw_p(p++, 0x0002);
> -                                /* li a0,2                      */
> -    }
> -
> -    stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
> -
> -    stw_p(p++, NM_HI2(ENVP_VADDR - 64));
> -                                /* lui sp,%hi(ENVP_VADDR - 64)   */
> -
> -    stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
> -                                /* ori sp,sp,%lo(ENVP_VADDR - 64) */
> -
> -    stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
> -
> -    stw_p(p++, NM_HI2(ENVP_VADDR));
> -                                /* lui a1,%hi(ENVP_VADDR)        */
> -
> -    stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
> -                                /* ori a1,a1,%lo(ENVP_VADDR)     */
> -
> -    stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
> -
> -    stw_p(p++, NM_HI2(ENVP_VADDR + 8));
> -                                /* lui a2,%hi(ENVP_VADDR + 8)    */
> -
> -    stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
> -                                /* ori a2,a2,%lo(ENVP_VADDR + 8) */
> -
> -    stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
> -
> -    stw_p(p++, NM_HI2(loaderparams.ram_low_size));
> -                                /* lui a3,%hi(loaderparams.ram_low_size) */
> -
> -    stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
> -                                /* ori a3,a3,%lo(loaderparams.ram_low_size) */
>   
>   #if TARGET_BIG_ENDIAN
>   #define cpu_to_gt32 cpu_to_le32
> @@ -719,20 +674,19 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>                        cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
>                        cpu_to_gt32(0x0bc00000 << 3));
>   
> -    p = v;
> -
>   #undef cpu_to_gt32
>   
> -    stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
> -
> -    stw_p(p++, NM_HI2(kernel_entry));
> -                                /* lui t9,%hi(kernel_entry)     */
> -
> -    stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
> -                                /* ori t9,t9,%lo(kernel_entry)  */
> -
> -    stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
> -                                /* jalrc   t8                   */
> +    bl_gen_jump_kernel(&v,
> +                       true, ENVP_VADDR - 64,
> +                       /*
> +                        * If semihosting is used, arguments have already been
> +                        * passed, so we preserve $a0.
> +                        */
> +                       !semihosting_get_argc(), 2,
> +                       true, ENVP_VADDR,
> +                       true, ENVP_VADDR + 8,
> +                       true, loaderparams.ram_low_size,
> +                       kernel_entry);
>   }
>   
>   /*
diff mbox series

Patch

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 451908b217..876bc26a7f 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -619,11 +619,6 @@  static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
     /* Small bootloader */
     p = (uint16_t *)base;
 
-#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
-#define NM_HI2(VAL) \
-          (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
-#define NM_LO(VAL)  ((VAL) & 0xfff)
-
     stw_p(p++, 0x2800); stw_p(p++, 0x001c);
                                 /* bc to_here */
     stw_p(p++, 0x8000); stw_p(p++, 0xc000);
@@ -642,46 +637,6 @@  static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
                                 /* nop */
 
     /* to_here: */
-    if (semihosting_get_argc()) {
-        /* Preserve a0 content as arguments have been passed    */
-        stw_p(p++, 0x8000); stw_p(p++, 0xc000);
-                                /* nop                          */
-    } else {
-        stw_p(p++, 0x0080); stw_p(p++, 0x0002);
-                                /* li a0,2                      */
-    }
-
-    stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
-
-    stw_p(p++, NM_HI2(ENVP_VADDR - 64));
-                                /* lui sp,%hi(ENVP_VADDR - 64)   */
-
-    stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
-                                /* ori sp,sp,%lo(ENVP_VADDR - 64) */
-
-    stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
-
-    stw_p(p++, NM_HI2(ENVP_VADDR));
-                                /* lui a1,%hi(ENVP_VADDR)        */
-
-    stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
-                                /* ori a1,a1,%lo(ENVP_VADDR)     */
-
-    stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
-
-    stw_p(p++, NM_HI2(ENVP_VADDR + 8));
-                                /* lui a2,%hi(ENVP_VADDR + 8)    */
-
-    stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
-                                /* ori a2,a2,%lo(ENVP_VADDR + 8) */
-
-    stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
-
-    stw_p(p++, NM_HI2(loaderparams.ram_low_size));
-                                /* lui a3,%hi(loaderparams.ram_low_size) */
-
-    stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
-                                /* ori a3,a3,%lo(loaderparams.ram_low_size) */
 
 #if TARGET_BIG_ENDIAN
 #define cpu_to_gt32 cpu_to_le32
@@ -719,20 +674,19 @@  static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
                      cpu_to_gt32(0x0bc00000 << 3));
 
-    p = v;
-
 #undef cpu_to_gt32
 
-    stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
-
-    stw_p(p++, NM_HI2(kernel_entry));
-                                /* lui t9,%hi(kernel_entry)     */
-
-    stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
-                                /* ori t9,t9,%lo(kernel_entry)  */
-
-    stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
-                                /* jalrc   t8                   */
+    bl_gen_jump_kernel(&v,
+                       true, ENVP_VADDR - 64,
+                       /*
+                        * If semihosting is used, arguments have already been
+                        * passed, so we preserve $a0.
+                        */
+                       !semihosting_get_argc(), 2,
+                       true, ENVP_VADDR,
+                       true, ENVP_VADDR + 8,
+                       true, loaderparams.ram_low_size,
+                       kernel_entry);
 }
 
 /*