diff mbox series

[PATCH-for-8.0,v2,05/11] hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator

Message ID 20221211204533.85359-6-philmd@linaro.org (mailing list archive)
State New, archived
Headers show
Series hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API | expand

Commit Message

Philippe Mathieu-Daudé Dec. 11, 2022, 8:45 p.m. UTC 
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

Comments

Richard Henderson Dec. 12, 2022, 1:55 p.m. UTC | #1 
On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/mips/bootloader.c | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> 
> diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
> index 9fc926d83f..1dd6ef2096 100644
> --- a/hw/mips/bootloader.c
> +++ b/hw/mips/bootloader.c
> @@ -129,7 +129,17 @@ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
>   
>   static void bl_gen_jalr(void **p, bl_reg rs)
>   {
> -    bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
> +    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
> +        uint32_t insn = 0;
> +
> +        insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
> +        insn = deposit32(insn, 21, 5, BL_REG_RA);
> +        insn = deposit32(insn, 16, 5, rs);
> +
> +        st_nm32_p(p, insn);
> +    } else {
> +        bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
> +    }
>   }
>   
>   static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
diff mbox series

Patch

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 9fc926d83f..1dd6ef2096 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -129,7 +129,17 @@  static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
 
 static void bl_gen_jalr(void **p, bl_reg rs)
 {
-    bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
+    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+        uint32_t insn = 0;
+
+        insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
+        insn = deposit32(insn, 21, 5, BL_REG_RA);
+        insn = deposit32(insn, 16, 5, rs);
+
+        st_nm32_p(p, insn);
+    } else {
+        bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
+    }
 }
 
 static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)