diff mbox series

[PATCH-for-8.0,v2,08/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)

Message ID 20221211204533.85359-9-philmd@linaro.org (mailing list archive)
State New, archived
Headers show
Series hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API | expand

Commit Message

Philippe Mathieu-Daudé Dec. 11, 2022, 8:45 p.m. UTC 
Part 3/5: Convert PCI0 I/O BAR setup

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 40 ++++++++--------------------------------
 1 file changed, 8 insertions(+), 32 deletions(-)

Comments

Richard Henderson Dec. 12, 2022, 2:37 p.m. UTC | #1 
On 12/11/22 14:45, Philippe Mathieu-Daudé wrote:
> Part 3/5: Convert PCI0 I/O BAR setup
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> ---
>   hw/mips/malta.c | 40 ++++++++--------------------------------
>   1 file changed, 8 insertions(+), 32 deletions(-)
> 
> diff --git a/hw/mips/malta.c b/hw/mips/malta.c
> index 3e80a12221..16161b1b03 100644
> --- a/hw/mips/malta.c
> +++ b/hw/mips/malta.c
> @@ -685,9 +685,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       /*
>        * Load BAR registers as done by YAMON:
> -     *
> -     *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
> -     *
>        */
>       stw_p(p++, 0xe040); stw_p(p++, 0x0681);
>                                   /* lui t1, %hi(0xb4000000)      */
> @@ -707,21 +704,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       stw_p(p++, 0xe020); stw_p(p++, 0x0801);
>                                   /* lui t0, %hi(0xc0000000)      */
> -
> -    /* 0x48 corresponds to GT_PCI0IOLD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
> -                                /* sw t0, 0x48(t1)              */
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x0800);
> -                                /* lui t0, %hi(0x40000000)      */
> -
> -    /* 0x50 corresponds to GT_PCI0IOHD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
> -                                /* sw t0, 0x50(t1)              */
> -
> -    stw_p(p++, 0xe020); stw_p(p++, 0x0001);
> -                                /* lui t0, %hi(0x80000000)      */
> -
>   #else
>   #define cpu_to_gt32 cpu_to_be32
>   
> @@ -738,23 +720,17 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
>   
>       stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
>                                   /* addiu[32] t0, $0, 0xc0       */
> -
> -    /* 0x48 corresponds to GT_PCI0IOLD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
> -                                /* sw t0, 0x48(t1)              */
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x0040);
> -                                /* addiu[32] t0, $0, 0x40       */
> -
> -    /* 0x50 corresponds to GT_PCI0IOHD                          */
> -    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
> -                                /* sw t0, 0x50(t1)              */
> -
> -    stw_p(p++, 0x0020); stw_p(p++, 0x0080);
> -                                /* addiu[32] t0, $0, 0x80       */
>   #endif
>       v = p;
>   
> +    /* setup PCI0 io window to 0x18000000-0x181fffff */
> +    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
> +                     cpu_to_gt32(0x18000000 << 3));
> +    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
> +                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
> +                     cpu_to_gt32(0x08000000 << 3));
> +
>       /* setup PCI0 mem windows */
>       bl_gen_write_u32(&v, /* GT_PCI0M0LD */
>                        cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
diff mbox series

Patch

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 3e80a12221..16161b1b03 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -685,9 +685,6 @@  static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     /*
      * Load BAR registers as done by YAMON:
-     *
-     *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
-     *
      */
     stw_p(p++, 0xe040); stw_p(p++, 0x0681);
                                 /* lui t1, %hi(0xb4000000)      */
@@ -707,21 +704,6 @@  static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     stw_p(p++, 0xe020); stw_p(p++, 0x0801);
                                 /* lui t0, %hi(0xc0000000)      */
-
-    /* 0x48 corresponds to GT_PCI0IOLD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
-                                /* sw t0, 0x48(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0800);
-                                /* lui t0, %hi(0x40000000)      */
-
-    /* 0x50 corresponds to GT_PCI0IOHD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
-                                /* sw t0, 0x50(t1)              */
-
-    stw_p(p++, 0xe020); stw_p(p++, 0x0001);
-                                /* lui t0, %hi(0x80000000)      */
-
 #else
 #define cpu_to_gt32 cpu_to_be32
 
@@ -738,23 +720,17 @@  static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
 
     stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
                                 /* addiu[32] t0, $0, 0xc0       */
-
-    /* 0x48 corresponds to GT_PCI0IOLD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9048);
-                                /* sw t0, 0x48(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x0040);
-                                /* addiu[32] t0, $0, 0x40       */
-
-    /* 0x50 corresponds to GT_PCI0IOHD                          */
-    stw_p(p++, 0x8422); stw_p(p++, 0x9050);
-                                /* sw t0, 0x50(t1)              */
-
-    stw_p(p++, 0x0020); stw_p(p++, 0x0080);
-                                /* addiu[32] t0, $0, 0x80       */
 #endif
     v = p;
 
+    /* setup PCI0 io window to 0x18000000-0x181fffff */
+    bl_gen_write_u32(&v, /* GT_PCI0IOLD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+                     cpu_to_gt32(0x18000000 << 3));
+    bl_gen_write_u32(&v, /* GT_PCI0IOHD */
+                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+                     cpu_to_gt32(0x08000000 << 3));
+
     /* setup PCI0 mem windows */
     bl_gen_write_u32(&v, /* GT_PCI0M0LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),