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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:23 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 04/15] hw/riscv/boot.c: make riscv_find_firmware() static Date: Wed, 21 Dec 2022 15:22:49 -0300 Message-Id: <20221221182300.307900-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The only caller is riscv_find_and_load_firmware(), which is in the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/boot.c | 44 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ebd351c840..7361d5c0d8 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -75,6 +75,28 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, } } +static char *riscv_find_firmware(const char *firmware_filename) +{ + char *filename; + + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); + if (filename == NULL) { + if (!qtest_enabled()) { + /* + * We only ship OpenSBI binary bios images in the QEMU source. + * For machines that use images other than the default bios, + * running QEMU test will complain hence let's suppress the error + * report for QEMU testing. + */ + error_report("Unable to load the RISC-V firmware \"%s\"", + firmware_filename); + exit(1); + } + } + + return filename; +} + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr, @@ -104,28 +126,6 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, return firmware_end_addr; } -char *riscv_find_firmware(const char *firmware_filename) -{ - char *filename; - - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); - if (filename == NULL) { - if (!qtest_enabled()) { - /* - * We only ship OpenSBI binary bios images in the QEMU source. - * For machines that use images other than the default bios, - * running QEMU test will complain hence let's suppress the error - * report for QEMU testing. - */ - error_report("Unable to load the RISC-V firmware \"%s\"", - firmware_filename); - exit(1); - } - } - - return filename; -} - target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 93e5f8760d..c03e4e74c5 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -37,7 +37,6 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -char *riscv_find_firmware(const char *firmware_filename); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb);