| Message ID | 20221223180016.2068508-15-christoph.muellner@vrull.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for the T-Head vendor extensions | expand |
On Sat, Dec 24, 2022 at 4:07 AM Christoph Muellner <christoph.muellner@vrull.eu> wrote: > > From: Christoph Müllner <christoph.muellner@vrull.eu> > > This patch adds support for the XTheadFmv ISA extension. > The patch uses the T-Head specific decoder and translation. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++ > target/riscv/translate.c | 6 +-- > target/riscv/xthead.decode | 4 ++ > 5 files changed, 55 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d3d8587710..d3f711cc41 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), > ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), > ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), > + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), > ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), > ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), > ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), > @@ -1107,6 +1108,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), > DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), > + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), > DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), > DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), > DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 28184bbe40..154c16208a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -473,6 +473,7 @@ struct RISCVCPUConfig { > bool ext_xtheadcmo; > bool ext_xtheadcondmov; > bool ext_xtheadfmemidx; > + bool ext_xtheadfmv; > bool ext_xtheadmac; > bool ext_xtheadmemidx; > bool ext_xtheadmempair; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc > index dc1a11070e..12d5af4f75 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -52,6 +52,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADFMV(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADMAC(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadmac) { \ > return false; \ > @@ -457,6 +463,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) > return gen_fstore_idx(ctx, a, MO_TEUL, true); > } > > +/* XTheadFmv */ > + > +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) > +{ > + REQUIRE_XTHEADFMV(ctx); > + REQUIRE_32BIT(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + > + TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + > + tcg_gen_extu_tl_i64(t1, src1); > + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); > + tcg_temp_free_i64(t1); > + mark_fs_dirty(ctx); > + return true; > +} > + > +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) > +{ > + REQUIRE_XTHEADFMV(ctx); > + REQUIRE_32BIT(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + TCGv dst; > + TCGv_i64 t1; > + > + dst = dest_gpr(ctx, a->rd); > + t1 = tcg_temp_new_i64(); > + > + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); > + tcg_gen_trunc_i64_tl(dst, t1); > + gen_set_gpr(ctx, a->rd, dst); > + tcg_temp_free_i64(t1); > + mark_fs_dirty(ctx); > + return true; > +} > + > /* XTheadMac */ > > static bool gen_th_mac(DisasContext *ctx, arg_r *a, > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index fb77df721e..1c54c3c67d 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -130,9 +130,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > ctx->cfg_ptr->ext_xtheadcondmov || > - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || > - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || > - ctx->cfg_ptr->ext_xtheadsync; > + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || > + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || > + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 81daf1d694..d1d104bcf2 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx > th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx > th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx > > +# XTheadFmv > +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 > +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 > + > # XTheadMac > th_mula 00100 00 ..... ..... 001 ..... 0001011 @r > th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r > -- > 2.38.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d3d8587710..d3f711cc41 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), @@ -1107,6 +1108,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 28184bbe40..154c16208a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadfmemidx; + bool ext_xtheadfmv; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index dc1a11070e..12d5af4f75 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) +#define REQUIRE_XTHEADFMV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -457,6 +463,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) return gen_fstore_idx(ctx, a, MO_TEUL, true); } +/* XTheadFmv */ + +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t1, src1); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + TCGv dst; + TCGv_i64 t1; + + dst = dest_gpr(ctx, a->rd); + t1 = tcg_temp_new_i64(); + + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); + tcg_gen_trunc_i64_tl(dst, t1); + gen_set_gpr(ctx, a->rd, dst); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + /* XTheadMac */ static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fb77df721e..1c54c3c67d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,9 +130,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 81daf1d694..d1d104bcf2 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx +# XTheadFmv +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r