@@ -86,7 +86,7 @@ static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
return addr;
}
-/* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */
+/* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */
static target_ulong read_p3_0(CPUHexagonState *env)
{
int32_t control_reg = 0;
@@ -102,7 +102,7 @@ static void print_reg(FILE *f, CPUHexagonState *env, int regnum)
{
target_ulong value;
- if (regnum == HEX_REG_P3_0) {
+ if (regnum == HEX_REG_P3_0_ALIASED) {
value = read_p3_0(env);
} else {
value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum])
@@ -198,7 +198,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)
print_reg(f, env, HEX_REG_M0);
print_reg(f, env, HEX_REG_M1);
print_reg(f, env, HEX_REG_USR);
- print_reg(f, env, HEX_REG_P3_0);
+ print_reg(f, env, HEX_REG_P3_0_ALIASED);
print_reg(f, env, HEX_REG_GP);
print_reg(f, env, HEX_REG_UGP);
print_reg(f, env, HEX_REG_PC);
@@ -163,7 +163,7 @@ static inline void gen_read_p3_0(TCGv control_reg)
/*
* Certain control registers require special handling on read
- * HEX_REG_P3_0 aliased to the predicate registers
+ * HEX_REG_P3_0_ALIASED aliased to the predicate registers
* -> concat the 4 predicate registers together
* HEX_REG_PC actual value stored in DisasContext
* -> assign from ctx->base.pc_next
@@ -173,7 +173,7 @@ static inline void gen_read_p3_0(TCGv control_reg)
static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
TCGv dest)
{
- if (reg_num == HEX_REG_P3_0) {
+ if (reg_num == HEX_REG_P3_0_ALIASED) {
gen_read_p3_0(dest);
} else if (reg_num == HEX_REG_PC) {
tcg_gen_movi_tl(dest, ctx->base.pc_next);
@@ -194,7 +194,7 @@ static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
TCGv_i64 dest)
{
- if (reg_num == HEX_REG_P3_0) {
+ if (reg_num == HEX_REG_P3_0_ALIASED) {
TCGv p3_0 = tcg_temp_new();
gen_read_p3_0(p3_0);
tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
@@ -238,7 +238,7 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv control_reg)
/*
* Certain control registers require special handling on write
- * HEX_REG_P3_0 aliased to the predicate registers
+ * HEX_REG_P3_0_ALIASED aliased to the predicate registers
* -> break the value across 4 predicate registers
* HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
* -> clear the changes
@@ -246,7 +246,7 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv control_reg)
static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
TCGv val)
{
- if (reg_num == HEX_REG_P3_0) {
+ if (reg_num == HEX_REG_P3_0_ALIASED) {
gen_write_p3_0(ctx, val);
} else {
gen_log_reg_write(reg_num, val);
@@ -266,7 +266,7 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
TCGv_i64 val)
{
- if (reg_num == HEX_REG_P3_0) {
+ if (reg_num == HEX_REG_P3_0_ALIASED) {
TCGv val32 = tcg_temp_new();
tcg_gen_extrl_i64_i32(val32, val);
gen_write_p3_0(ctx, val32);
@@ -58,7 +58,7 @@ enum {
HEX_REG_LC0 = 33,
HEX_REG_SA1 = 34,
HEX_REG_LC1 = 35,
- HEX_REG_P3_0 = 36,
+ HEX_REG_P3_0_ALIASED = 36,
HEX_REG_M0 = 38,
HEX_REG_M1 = 39,
HEX_REG_USR = 40,