| Message ID | 20221229152325.32041-5-philmd@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/arm/aspeed_ast10x0: Map more peripherals & few more fixes | expand |
On Thu, Dec 29, 2022 at 04:23:20PM +0100, Philippe Mathieu-Daudé wrote: > Since I don't have access to the datasheet, the relevant > values were found in: > https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c > index d7dbc1a801..53ea6d471f 100644 > --- a/hw/arm/aspeed_ast10x0.c > +++ b/hw/arm/aspeed_ast10x0.c > @@ -54,6 +54,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { > [ASPEED_DEV_WDT] = 0x7E785000, > [ASPEED_DEV_LPC] = 0x7E789000, > [ASPEED_DEV_PECI] = 0x7E78B000, > + [ASPEED_DEV_I3C] = 0x7E7A0000, > [ASPEED_DEV_I2C] = 0x7E7B0000, > }; > > @@ -89,6 +90,7 @@ static const int aspeed_soc_ast1030_irqmap[] = { > [ASPEED_DEV_ADC] = 46, > [ASPEED_DEV_SPI1] = 65, > [ASPEED_DEV_SPI2] = 66, > + [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */ > [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ > [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ > [ASPEED_DEV_UDC] = 9, > @@ -130,6 +132,8 @@ static void aspeed_soc_ast1030_init(Object *obj) > snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); > object_initialize_child(obj, "i2c", &s->i2c, typename); > > + object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); > + > snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); > object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); > > @@ -240,6 +244,18 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) > sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); > } > > + /* I3C */ > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { > + return; > + } > + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); > + for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { > + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), > + sc->irqmap[ASPEED_DEV_I3C] + i); > + /* The AST1030 I2C controller has one IRQ per bus. */ Should this comment be I2C or I3C? Otherwise looks good! Reviewed-by: Peter Delevoryas <peter@pjd.dev> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); > + } > + > /* PECI */ > if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { > return; > -- > 2.38.1 k
On 29/12/22 21:46, Peter Delevoryas wrote: > On Thu, Dec 29, 2022 at 04:23:20PM +0100, Philippe Mathieu-Daudé wrote: >> Since I don't have access to the datasheet, the relevant >> values were found in: >> https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> @@ -240,6 +244,18 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) >> sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); >> } >> >> + /* I3C */ >> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { >> + return; >> + } >> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); >> + for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { >> + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), >> + sc->irqmap[ASPEED_DEV_I3C] + i); >> + /* The AST1030 I2C controller has one IRQ per bus. */ > > Should this comment be I2C or I3C? Oops indeed, copy/paste leftover :) > Reviewed-by: Peter Delevoryas <peter@pjd.dev> Thanks!
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index d7dbc1a801..53ea6d471f 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -54,6 +54,7 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = { [ASPEED_DEV_WDT] = 0x7E785000, [ASPEED_DEV_LPC] = 0x7E789000, [ASPEED_DEV_PECI] = 0x7E78B000, + [ASPEED_DEV_I3C] = 0x7E7A0000, [ASPEED_DEV_I2C] = 0x7E7B0000, }; @@ -89,6 +90,7 @@ static const int aspeed_soc_ast1030_irqmap[] = { [ASPEED_DEV_ADC] = 46, [ASPEED_DEV_SPI1] = 65, [ASPEED_DEV_SPI2] = 66, + [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */ [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ [ASPEED_DEV_UDC] = 9, @@ -130,6 +132,8 @@ static void aspeed_soc_ast1030_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); object_initialize_child(obj, "i2c", &s->i2c, typename); + object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); + snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); @@ -240,6 +244,18 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); } + /* I3C */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); + for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { + qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m), + sc->irqmap[ASPEED_DEV_I3C] + i); + /* The AST1030 I2C controller has one IRQ per bus. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); + } + /* PECI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { return;
Since I don't have access to the datasheet, the relevant values were found in: https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)