From patchwork Thu Jan 19 21:37:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13108821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84DF6C46467 for ; Thu, 19 Jan 2023 21:37:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIcb9-0006HK-TM; Thu, 19 Jan 2023 16:37:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIcb2-0006Fp-Vr for qemu-devel@nongnu.org; Thu, 19 Jan 2023 16:37:25 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIcaz-0001o6-BR for qemu-devel@nongnu.org; Thu, 19 Jan 2023 16:37:19 -0500 Received: by mail-oi1-x244.google.com with SMTP id v17so2846676oie.5 for ; Thu, 19 Jan 2023 13:37:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j2cyku08fqdVqnCSE5BwHBuZAdyuCmWqjhgrF9jsYIo=; b=hypyzoApJRVq9NAivJ4Rxtplue/+ny/3WLyg4tgPMAbcbMqrPpH2BhuTWBqaC281zl 7YaIPFdpGfVArftW2LlR8iTALlCQZCtwHq7PIh+Jhox6dANRafsnUvZDGiLj7LPllkgV 1PDRje8CSuVMkDPusBh0nEowSIi55NPFTWE2PEfNMHaEO4THnjOKb9sJ7sIw1Sr1kosr 9vXav49cIbmyQkECz2gY+dU3SKBEajdjF7U2xT+6Vm60lMzMv7ipuvpvun72bd9x9FFU O1GLoukseMjPswva7wNEQlM+kL4cvzzz2A+WJbEaFFLPGuLds6L/+K40Eq835E2u3M7m 0VLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j2cyku08fqdVqnCSE5BwHBuZAdyuCmWqjhgrF9jsYIo=; b=38AxDoDb+doLaOcMnlP2LfLVCWUTKwHCjXhg8zTEyNecGPhjIOK2708n9RKA8A9RLo 2xNRhh30fMRWfY5peeNBPryfFRbkLy4LwFyh6nWOW3FWHqjxcySMhyf8ZqpuSAuMCsa6 TP0eA/qJ8lOtC/XlxCty++cyWS+8ellezoQRgtZpAgW4zpb5dTb3H3yfUCOXRKAfOH6I 91mHWYFudMnNMgowuk3Rxqs4bthLSNGLvatBRwjKL95MtUqqbU+ZvPJ6suDMh62qERlJ utWAC0qOOOEIXDZObA490TJLhGxxlhiM11HOFk9p2XGZMakYDV1xY5vMMkZAY9u+DWcz oM6w== X-Gm-Message-State: AFqh2krrsYF8COGoIuz4w44ok3GBRuQpOY+BEh3lR0eX9WldtoxgXSRv lNH/kvrQIl+bVb6XPPDj3dKdBNq5TVojHNZAoAA= X-Google-Smtp-Source: AMrXdXtUU3vPA2w8RIcE0TbyKHu87YTb71iEm9aF7hCb+7VudwLye+tB2ijCcgpUh1hH/KDZlhre5A== X-Received: by 2002:aca:b483:0:b0:35e:574c:c244 with SMTP id d125-20020acab483000000b0035e574cc244mr5364994oif.7.1674164234361; Thu, 19 Jan 2023 13:37:14 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id c132-20020aca358a000000b003646062e83bsm13664472oia.29.2023.01.19.13.37.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 13:37:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v9 1/3] hw/riscv: clear kernel_entry higher bits from load_elf_ram_sym() Date: Thu, 19 Jan 2023 18:37:05 -0300 Message-Id: <20230119213707.651533-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119213707.651533-1-dbarboza@ventanamicro.com> References: <20230119213707.651533-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU guest happens to be running in a hypervisor that are using 64 bits to encode its address, kernel_entry can be padded with '1's and create problems [1]. Use a translate_fn() callback to be called by load_elf_ram_sym() and return only the 32 bits address if we're running a 32 bit CPU. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html Suggested-by: Philippe Mathieu-Daudé Suggested-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 20 +++++++++++++++++++- hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 3 ++- include/hw/riscv/boot.h | 1 + 8 files changed, 32 insertions(+), 7 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..46fc7adccf 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,7 +173,24 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) +{ + RISCVHartArrayState *harts = opaque; + + if (riscv_is_32bit(harts)) { + /* + * For 32 bit CPUs, kernel_load_base is sign-extended + * (i.e. it can be padded with '1's) by load_elf(). + * Remove the sign extension by truncating to 32-bit. + */ + return extract64(addr, 0, 32); + } + + return addr; +} + target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { @@ -189,7 +206,8 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to have * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, + translate_kernel_address, harts, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { return kernel_load_base; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..bdefeb3cbb 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,7 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..2731138c41 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[IBEX_DEV_RAM].base, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..1a7d381514 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2fb6ee231f..83dfe09877 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,7 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index badc11ec43..2bcc50d90d 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -305,7 +305,8 @@ static void spike_board_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + kernel_entry = riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, htif_symbol_callback); if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a11b4b010..ac173a6ed6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1274,7 +1274,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..105706bf25 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong firmware_end_addr, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);