| Message ID | 20230127175507.2895013-2-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Implement FEAT_FGT fine-grained traps | expand |
On 1/27/23 07:54, Peter Maydell wrote: > The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT > S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name > them AT S1E1R and AT S1E1W (which are entirely different > instructions). Fix the names. > > (This has no guest-visible effect as the names are for debug purposes > only.) > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 72b37b7cf17..ccb7d1e1712 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -7734,11 +7734,11 @@ static const ARMCPRegInfo vhe_reginfo[] = { > > #ifndef CONFIG_USER_ONLY > static const ARMCPRegInfo ats1e1_reginfo[] = { > - { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, > + { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, > .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, > .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, > .writefn = ats_write64 }, > - { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, > + { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, > .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, > .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, > .writefn = ats_write64 },
diff --git a/target/arm/helper.c b/target/arm/helper.c index 72b37b7cf17..ccb7d1e1712 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7734,11 +7734,11 @@ static const ARMCPRegInfo vhe_reginfo[] = { #ifndef CONFIG_USER_ONLY static const ARMCPRegInfo ats1e1_reginfo[] = { - { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, + { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, - { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, + { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name them AT S1E1R and AT S1E1W (which are entirely different instructions). Fix the names. (This has no guest-visible effect as the names are for debug purposes only.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)