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[77.13.82.236]) by smtp.gmail.com with ESMTPSA id c10-20020a056402100a00b00483dd234ac6sm8178318edu.96.2023.01.31.03.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 03:53:53 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Igor Mammedov , Richard Henderson , Ani Sinha , "Michael S. Tsirkin" , Paolo Bonzini , BALATON Zoltan , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , Laurent Vivier , Sunil Muthuswamy , qemu-trivial@nongnu.org, Bernhard Beschow Subject: [PATCH v2 04/20] hw/i386/pc_q35: Resolve redundant q35_host variable Date: Tue, 31 Jan 2023 12:53:10 +0100 Message-Id: <20230131115326.12454-5-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131115326.12454-1-shentey@gmail.com> References: <20230131115326.12454-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=shentey@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The variable is redundant to "phb" and is never used by its real type. Signed-off-by: Bernhard Beschow Reviewed-by: Thomas Huth --- hw/i386/pc_q35.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 351ef25f69..88324af91f 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -118,8 +118,7 @@ static void pc_q35_init(MachineState *machine) PCMachineState *pcms = PC_MACHINE(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms = X86_MACHINE(machine); - Q35PCIHost *q35_host; - PCIHostState *phb; + Object *phb; PCIBus *host_bus; PCIDevice *lpc; DeviceState *lpc_dev; @@ -206,10 +205,10 @@ static void pc_q35_init(MachineState *machine) } /* create pci host bus */ - q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); + phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); if (pcmc->pci_enabled) { - pci_hole64_size = object_property_get_uint(OBJECT(q35_host), + pci_hole64_size = object_property_get_uint(phb, PCI_HOST_PROP_PCI_HOLE64_SIZE, &error_abort); } @@ -218,23 +217,22 @@ static void pc_q35_init(MachineState *machine) pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, pci_hole64_size); - object_property_add_child(OBJECT(machine), "q35", OBJECT(q35_host)); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, + object_property_add_child(OBJECT(machine), "q35", phb); + object_property_set_link(phb, MCH_HOST_PROP_RAM_MEM, OBJECT(ram_memory), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, + object_property_set_link(phb, MCH_HOST_PROP_PCI_MEM, OBJECT(pci_memory), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, + object_property_set_link(phb, MCH_HOST_PROP_SYSTEM_MEM, OBJECT(get_system_memory()), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, + object_property_set_link(phb, MCH_HOST_PROP_IO_MEM, OBJECT(system_io), NULL); - object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, + object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, x86ms->below_4g_mem_size, NULL); - object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, + object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); /* pci */ - sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); - phb = PCI_HOST_BRIDGE(q35_host); - host_bus = phb->bus; + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true,