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Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman Subject: [PATCH v5 3/8] igb: add ICR_RXDW Date: Thu, 2 Feb 2023 08:26:43 +0100 Message-Id: <20230202072648.4743-4-sriram.yagnaraman@est.tech> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202072648.4743-1-sriram.yagnaraman@est.tech> References: <20230202072648.4743-1-sriram.yagnaraman@est.tech> X-ClientProxiedBy: GV3P280CA0004.SWEP280.PROD.OUTLOOK.COM (2603:10a6:150:b::18) To DBBP189MB1433.EURP189.PROD.OUTLOOK.COM (2603:10a6:10:1e7::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DBBP189MB1433:EE_|DB4P189MB2389:EE_ X-MS-Office365-Filtering-Correlation-Id: f434395d-d4d4-48c0-d9e4-08db04f01425 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZNmf/4+x1IWEPxMKvJPKmVJwz9TfDZ2nFyAx+ReHKw7gSuM5bQQzMy/nnGqcxzR9/ID2ip0yo4oGfqMgdY2oH871UxqVqSIrGNBryYi7hJ/cNS11rYruu2C1/+vRriN1QDZ1dUhxtJanZDZptvnqvAMZzdIeSzmE7uxfuoPIzdanGI75T+oR4Ft1H024F3o77h0cDncAUSnk7bCO8qfZuiRyYe59WfTDgwTyCT5SVHX40WNtImifV6yOXiymNO9uu3jEw3bK+Sb1BgvNNRAbQ0LttaabncoHGNFRrqRd0A6oSlcs9c1e018+RDi1By6oQUaAKERGl+qEeAucFvJBw+LhppD0tNal1FQgDKPaTNfRs3mrX9wyLy7soFKXnt3gIR6zdFB98NhkflH4zq25GTiBlrwe7/farnhWInGJNhKXPDMb3+KteMyepbvuSv86ven/ASNe/91LDqLNXQLL14TvUBie16O2dR0+c2CciMErWAIHfGpyT4wS2HABT5RaOKvyiL5ZU2oGoR+tZtbDGmvYPlZX/rl543VYVPOSy037jRutrcLamQ2EkWNV3fOj+yLoeVrwN5QGPY3kaqMeHP6XkK/CVb7FJHgTsSyn5NpGnTqMLZv8Vba6vrclLfZJg0SyhJLIAKMTFp+3H2wiAHOSHoEDcP9ooJ3fztHgxXzhE8p9eFriuK4Pzs0ARBQLEDNg0JJhdMTJX4dr7A213WtmmAtJ7hZSYOaGY8UlKo8= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=sriram.yagnaraman@est.tech; helo=EUR05-VI1-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IGB uses RXDW ICR bit to indicate that rx descriptor has been written back. This is the same as RXT0 bit in older HW. Signed-off-by: Sriram Yagnaraman --- hw/net/e1000x_regs.h | 4 ++++ hw/net/igb_core.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h index fb5b861135..f509db73a7 100644 --- a/hw/net/e1000x_regs.h +++ b/hw/net/e1000x_regs.h @@ -335,6 +335,7 @@ #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ #define E1000_ICR_RXO 0x00000040 /* rx overrun */ #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_RXDW 0x00000080 /* rx desc written back */ #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ @@ -378,6 +379,7 @@ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -407,6 +409,7 @@ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -441,6 +444,7 @@ #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index b484e6ac30..1ddf54f630 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -1582,7 +1582,7 @@ igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, n |= E1000_ICS_RXDMT0; } - n |= E1000_ICR_RXT0; + n |= E1000_ICR_RXDW; trace_e1000e_rx_written_to_guest(rxr.i->idx); }