From patchwork Thu Feb 2 09:49:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13125642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBA35C63797 for ; Thu, 2 Feb 2023 09:44:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNW8a-0007Kc-AB; Thu, 02 Feb 2023 04:44:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8X-0007FR-Uq for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:44:09 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNW8W-0006Pg-BB for qemu-devel@nongnu.org; Thu, 02 Feb 2023 04:44:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675331048; x=1706867048; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uLL+NWRhAQrmrOXrW9mrGp0p9bgRS48bvW90TKnZBAM=; b=jOrb500suwK4IYaPCIItGB+irpwlFpMvOCw2B3q6gVJsmJuiVa57LPw2 waNCufiUmJfjXAA+kNu2zhT46WeGLEMM8JtlAa3dgoomX9f9uk1Flg/+i ZEwMdt/66GZiNCd3iSWi+VNmRJ4gEPF1uzA4Yvuqw1Wra3y9UQOASo9zI lsca4Gvpqyq+Sev4bVzKYDeRaD5QVFLf4V9Hg+fKm+Wh+P78krfq/+RGo 27Y9bZwEY6OMZDGSld0FCEcHWoORIhwkfBUMs8M5g52uNto7lUt9st/1z cK1UnoKxjlnu/CiWTw7gB72CJc/iNoPSOwFIxLVU9gabugbBemNDaMypf w==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="316402169" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="316402169" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2023 01:42:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807909500" X-IronPort-AV: E=Sophos;i="5.97,267,1669104000"; d="scan'208";a="807909500" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga001.fm.intel.com with ESMTP; 02 Feb 2023 01:42:41 -0800 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Zhao Liu Subject: [PATCH 17/18] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Date: Thu, 2 Feb 2023 17:49:28 +0800 Message-Id: <20230202094929.343799-18-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com> References: <20230202094929.343799-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Zhao Liu CPUID[0x8000001D].EAX[bits 25:14] is used to represent the cache topology for amd CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d691c02e3c06..5816dc99b1d4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -355,20 +355,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t sharing_apic_ids; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level == 3) { - sharing_apic_ids = 1 << apicid_die_offset(topo_info); - } else { - sharing_apic_ids = 1 << apicid_core_offset(topo_info); - } - *eax |= (sharing_apic_ids - 1) << 14; + *eax |= max_processor_ids_for_cache(cache, topo_info) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0);