[11/39] target/riscv: add zvkns cpu property

Commit Message

Lawrence Hunter Feb. 2, 2023, 12:42 p.m. UTC

From: Nazar Kazakov <[e-mail]>

Signed-off-by: Nazar Kazakov <[e-mail]>
---
 target/riscv/cpu.c | 3 ++-
 target/riscv/cpu.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 35790befc0..fd09822b4f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -101,6 +101,7 @@  static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
     ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
+    ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns),
     ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
@@ -797,7 +798,7 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
          * In principle zve*{x,d} would also suffice here, were they supported
          * in qemu
          */
-        if (cpu->cfg.ext_zvkb &&
+        if ((cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkns) &&
             !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_v)) {
             error_setg(
                 errp, "Vector crypto extensions require V or Zve* extensions");
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d4824ad0bb..56008ef9b9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,6 +462,7 @@  struct RISCVCPUConfig {
     bool ext_zve32f;
     bool ext_zve64f;
     bool ext_zvkb;
+    bool ext_zvkns;
     bool ext_zmmul;
     bool ext_smaia;
     bool ext_ssaia;