diff mbox series

[09/11] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()

Message ID 20230210133635.589647-10-dbarboza@ventanamicro.com (mailing list archive)
State New, archived
Headers show
Series enable write_misa() and RISCV_FEATURE_* cleanups | expand

Commit Message

Daniel Henrique Barboza Feb. 10, 2023, 1:36 p.m. UTC 
Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
riscv_isa_string().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/virt.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Weiwei Li Feb. 14, 2023, 3:23 p.m. UTC | #1 
On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
> riscv_isa_string().
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>   hw/riscv/virt.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 86c4adc0c9..8ab6a3ec16 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
>       bool is_32_bit = riscv_is_32bit(&s->soc[0]);
>   
>       for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
> +        RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
> +        RISCVCPUConfig cpu_cfg = cpu_ptr->cfg;

Adding cpu_cfg seems not very necessary.

Otherwise, Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

>           cpu_phandle = (*phandle)++;
>   
>           cpu_name = g_strdup_printf("/cpus/cpu@%d",
>               s->soc[socket].hartid_base + cpu);
>           qemu_fdt_add_subnode(ms->fdt, cpu_name);
> -        if (riscv_feature(&s->soc[socket].harts[cpu].env,
> -                          RISCV_FEATURE_MMU)) {
> +        if (cpu_cfg.mmu) {
>               qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
>                                       (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
>           } else {
>               qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
>                                       "riscv,none");
>           }
> -        name = riscv_isa_string(&s->soc[socket].harts[cpu]);
> +        name = riscv_isa_string(cpu_ptr);
>           qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
>           g_free(name);
>           qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
diff mbox series

Patch

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86c4adc0c9..8ab6a3ec16 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -232,20 +232,21 @@  static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
     bool is_32_bit = riscv_is_32bit(&s->soc[0]);
 
     for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+        RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
+        RISCVCPUConfig cpu_cfg = cpu_ptr->cfg;
         cpu_phandle = (*phandle)++;
 
         cpu_name = g_strdup_printf("/cpus/cpu@%d",
             s->soc[socket].hartid_base + cpu);
         qemu_fdt_add_subnode(ms->fdt, cpu_name);
-        if (riscv_feature(&s->soc[socket].harts[cpu].env,
-                          RISCV_FEATURE_MMU)) {
+        if (cpu_cfg.mmu) {
             qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                     (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
         } else {
             qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                     "riscv,none");
         }
-        name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+        name = riscv_isa_string(cpu_ptr);
         qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
         g_free(name);
         qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");