| Message ID | 20230210133635.589647-11-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | enable write_misa() and RISCV_FEATURE_* cleanups | expand |
On 2023/2/10 21:36, Daniel Henrique Barboza wrote: > RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use > the flag directly instead. > > With this change the enum is also removed. It is worth noticing that > this enum, and all the RISCV_FEATURES_* that were contained in it, > predates the existence of the cpu->cfg object. Today, using cpu->cfg is > an easier way to retrieve all the features and extensions enabled in the > hart. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li > --- > target/riscv/cpu.c | 4 ---- > target/riscv/cpu.h | 7 ------- > target/riscv/cpu_helper.c | 2 +- > target/riscv/csr.c | 4 ++-- > target/riscv/monitor.c | 2 +- > target/riscv/pmp.c | 2 +- > 6 files changed, 5 insertions(+), 16 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a803395ed1..2859ebc3e6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > > - if (cpu->cfg.mmu) { > - riscv_set_feature(env, RISCV_FEATURE_MMU); > - } > - > if (cpu->cfg.epmp && !cpu->cfg.pmp) { > /* > * Enhanced PMP should only be available > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 62919cd5cc..83a9fa38d9 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -81,13 +81,6 @@ > #define RVH RV('H') > #define RVJ RV('J') > > -/* S extension denotes that Supervisor mode exists, however it is possible > - to have a core that support S mode but does not have an MMU and there > - is currently no bit in misa to indicate whether an MMU exists or not > - so a cpu features bitfield is required, likewise for optional PMP support */ > -enum { > - RISCV_FEATURE_MMU, > -}; > > /* Privileged specification version */ > enum { > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 15d9542691..e76b206191 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > mode = PRV_U; > } > > - if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { > + if (mode == PRV_M || !riscv_cpu_cfg(env).mmu) { > *physical = addr; > *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; > return TRANSLATE_SUCCESS; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 3d55b1b138..9fb8e86b70 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2623,7 +2623,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno, > static RISCVException read_satp(CPURISCVState *env, int csrno, > target_ulong *val) > { > - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { > + if (!riscv_cpu_cfg(env).mmu) { > *val = 0; > return RISCV_EXCP_NONE; > } > @@ -2642,7 +2642,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, > { > target_ulong vm, mask; > > - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { > + if (!riscv_cpu_cfg(env).mmu) { > return RISCV_EXCP_NONE; > } > > diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c > index 236f93b9f5..b7b8d0614f 100644 > --- a/target/riscv/monitor.c > +++ b/target/riscv/monitor.c > @@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) > return; > } > > - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { > + if (!riscv_cpu_cfg(env).mmu) { > monitor_printf(mon, "S-mode MMU unavailable\n"); > return; > } > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index 1e7903dffa..c67de36942 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, > } > > if (size == 0) { > - if (riscv_feature(env, RISCV_FEATURE_MMU)) { > + if (riscv_cpu_cfg(env).mmu) { > /* > * If size is unknown (0), assume that all bytes > * from addr to the end of the page will be accessed.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a803395ed1..2859ebc3e6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.mmu) { - riscv_set_feature(env, RISCV_FEATURE_MMU); - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62919cd5cc..83a9fa38d9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,13 +81,6 @@ #define RVH RV('H') #define RVJ RV('J') -/* S extension denotes that Supervisor mode exists, however it is possible - to have a core that support S mode but does not have an MMU and there - is currently no bit in misa to indicate whether an MMU exists or not - so a cpu features bitfield is required, likewise for optional PMP support */ -enum { - RISCV_FEATURE_MMU, -}; /* Privileged specification version */ enum { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 15d9542691..e76b206191 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, mode = PRV_U; } - if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { + if (mode == PRV_M || !riscv_cpu_cfg(env).mmu) { *physical = addr; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3d55b1b138..9fb8e86b70 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2623,7 +2623,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno, static RISCVException read_satp(CPURISCVState *env, int csrno, target_ulong *val) { - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env).mmu) { *val = 0; return RISCV_EXCP_NONE; } @@ -2642,7 +2642,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, { target_ulong vm, mask; - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env).mmu) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 236f93b9f5..b7b8d0614f 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env).mmu) { monitor_printf(mon, "S-mode MMU unavailable\n"); return; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 1e7903dffa..c67de36942 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, } if (size == 0) { - if (riscv_feature(env, RISCV_FEATURE_MMU)) { + if (riscv_cpu_cfg(env).mmu) { /* * If size is unknown (0), assume that all bytes * from addr to the end of the page will be accessed.
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use the flag directly instead. With this change the enum is also removed. It is worth noticing that this enum, and all the RISCV_FEATURES_* that were contained in it, predates the existence of the cpu->cfg object. Today, using cpu->cfg is an easier way to retrieve all the features and extensions enabled in the hart. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 4 ---- target/riscv/cpu.h | 7 ------- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 4 ++-- target/riscv/monitor.c | 2 +- target/riscv/pmp.c | 2 +- 6 files changed, 5 insertions(+), 16 deletions(-)