From patchwork Fri Feb 10 13:36:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13135787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15731C636CD for ; Fri, 10 Feb 2023 13:37:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pQTaB-0005NM-Vi; Fri, 10 Feb 2023 08:36:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pQTaA-0005Mq-M2 for qemu-devel@nongnu.org; Fri, 10 Feb 2023 08:36:54 -0500 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pQTa9-0007Vp-1T for qemu-devel@nongnu.org; Fri, 10 Feb 2023 08:36:54 -0500 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-169ba826189so6691603fac.2 for ; Fri, 10 Feb 2023 05:36:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRs4VzXLgz+2ta5fdh+bco0FgUBmM+avNnvHl5gY0EE=; b=QKeE3v7wLmBLcj0ZFh/H3GG0jqG+LasZJJtg4oPCDxz/8roP1pJ1SIG4vq9yEX51jw reNiSWSzWfQJJ3f07qChs+RZrV+4csVHYDZ/8YCXKq91zOO86YJ/KnauURxkl5LJCJok Kboax1q1eSuXRDKnRjssHDHYsGu67Y9tIePqnQj+fqZ/zd8WX/MN3dmcBLnzzGIoKCU7 0NE/qWIiTigPDEogwGRf5hlNC+mst9loYpgCb11sRAJ9L0C4DMQn5sP2cdsSGAulnIHo 9BdS7/U3WqQuiXuZ747kf4np6Gh8nzVn2KfuWtJOadT7fsQPDenqzzRhZACiEn98Bro6 CUkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRs4VzXLgz+2ta5fdh+bco0FgUBmM+avNnvHl5gY0EE=; b=pRz9Aa+7UbCPnLFp8evaI138mmDHYYRl8r6ysn74SRjtp5JUPTt9JjRbwat9jgEkFr ejEyfPCW/V25ErPnsnrVVVk73yfjBDPgvXD81ukUXgtY8apSZspOjOslUZs5cEkBtMRY uBH+IHmcwFup8LQZJWszt8/VIWhY8TTQNdLWpqzJ0WuPAuFbUGLQ+a1ovxzwGmpQopER 1W7Vu17dbtIeV861JsWaBNJz5kYOQtATjvDsJI/vzpZl5UltLfCjBmoZNs9Qi+rCEkwx 8+GhpQ5qo7/rVq+8XK6cdCPhwFAFbF0gGJg3aHjw7tK1OrXsoeLzqGQi5fTY/bX6bTsF FXvQ== X-Gm-Message-State: AO0yUKWjjg8CzDpWCud16iAcPb4Qw8KFhNRCjoA5tPFgJ24QmWQYyDgB K6Eg0hq/X2nqJQIOsQ7e3HJRWymppBZ+VJIN X-Google-Smtp-Source: AK7set8NVUckYX0uP0U/a0jkU3RhXpF+VV86bhBIxOUCgGzQTdf/hMdu+K4NfzIhWd27K63+PjFaHg== X-Received: by 2002:a05:6870:d10d:b0:16a:b526:59a6 with SMTP id e13-20020a056870d10d00b0016ab52659a6mr4728524oac.43.1676036211523; Fri, 10 Feb 2023 05:36:51 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.19.125.138]) by smtp.gmail.com with ESMTPSA id s36-20020a05687050e400b0014474019e50sm1890570oaf.24.2023.02.10.05.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 05:36:51 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 05/11] target/riscv: remove RISCV_FEATURE_DEBUG Date: Fri, 10 Feb 2023 10:36:29 -0300 Message-Id: <20230210133635.589647-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230210133635.589647-1-dbarboza@ventanamicro.com> References: <20230210133635.589647-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 6 +----- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 3 +-- 5 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69fb9e123f..272cf1a8bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (cpu->cfg.debug) { riscv_trigger_init(env); } @@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.debug) { - riscv_set_feature(env, RISCV_FEATURE_DEBUG); - } - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 00a464c9c4..46de6f2f7f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_DEBUG }; /* Privileged specification version */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ad8d82662c..4cdd247c6c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } - if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4f9cc501b2..af4a44b33b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno) static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (riscv_cpu_cfg(env).debug) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c6ce318cce..4634968898 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = { static bool debug_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_feature(env, RISCV_FEATURE_DEBUG); + return cpu->cfg.debug; } static int debug_post_load(void *opaque, int version_id)