From patchwork Mon Feb 13 09:36:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13138020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7CCBC636D4 for ; Mon, 13 Feb 2023 09:31:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRVBB-0007OF-Mf; Mon, 13 Feb 2023 04:31:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRVAC-0006pK-0g for qemu-devel@nongnu.org; Mon, 13 Feb 2023 04:30:21 -0500 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRVA9-0006qi-VY for qemu-devel@nongnu.org; Mon, 13 Feb 2023 04:30:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676280617; x=1707816617; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h2l32Mxk3IIptSYvwOMjSG7Mq4ltZJOLf/uBlKfJWe8=; b=GTbgVFhZtp95/YOPWa2yZMrJtbGq+hlnIyJ63yvOvx7jKFQwl4fTrSJG D98cYA69sApv/IC8LFCxR/HfnprFHApNxF8ccXZU04WXR8OyVbjU6dBZ9 dWmrp76tnglB2y4U8rNFebDL8Izv+ixfrWp1LEWntnrCoKpi/t0tA/aJk XErB4PMwFF+kvpu2twme4v0Kv6637WjbYwK3+12dDFXH9Vbh1wFDMqikG qHYbEWbW9n4RsKqDUj96IAY1AX1iFj3mSWma8iCmaUDGJs2+ExE+Uu+cF CR9/byciT2PLPZpSykBcope4Y1yPCwpmmmHZ6Zak2I75YAZ1H2O8P/jpv Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="318875907" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="318875907" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2023 01:30:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="792660564" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="792660564" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by orsmga004.jf.intel.com with ESMTP; 13 Feb 2023 01:30:09 -0800 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster Cc: qemu-devel@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhuocheng Ding , Robert Hoo , Xiaoyao Li , Like Xu , Zhao Liu Subject: [PATCH RESEND 18/18] i386: Add new property to control L2 cache topo in CPUID.04H Date: Mon, 13 Feb 2023 17:36:25 +0800 Message-Id: <20230213093625.158170-19-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230213093625.158170-1-zhao1.liu@linux.intel.com> References: <20230213093625.158170-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Zhao Liu The property x-l2-cache-topo will be used to change the L2 cache topology in CPUID.04H. Now it allows user to set the L2 cache is shared in core level or cluster level. If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache topology will be overrided by the new topology setting. Here we expose to user "cluster" instead of "module", to be consistent with "cluster-id" naming. Since CPUID.04H is used by intel CPUs, this property is available on intel CPUs as for now. When necessary, it can be extended to CPUID.8000001DH for amd CPUs. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- target/i386/cpu.h | 2 ++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5816dc99b1d4..cf84c720a431 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -240,12 +240,15 @@ static uint32_t max_processor_ids_for_cache(CPUCacheInfo *cache, case CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case DIE: num_ids = 1 << apicid_die_offset(topo_info); break; default: /* - * Currently there is no use case for SMT, MODULE and PACKAGE, so use + * Currently there is no use case for SMT and PACKAGE, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -6633,6 +6636,33 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) env->cache_info_amd.l3_cache = &legacy_l3_cache; } + if (cpu->l2_cache_topo_level) { + /* + * FIXME: Currently only supports changing CPUID[4] (for intel), and + * will support changing CPUID[0x8000001D] when necessary. + */ + if (!IS_INTEL_CPU(env)) { + error_setg(errp, "only intel cpus supports x-l2-cache-topo"); + return; + } + + if (!strcmp(cpu->l2_cache_topo_level, "core")) { + env->cache_info_cpuid4.l2_cache->share_level = CORE; + } else if (!strcmp(cpu->l2_cache_topo_level, "cluster")) { + /* + * We expose to users "cluster" instead of "module", to be + * consistent with "cluster-id" naming. + */ + env->cache_info_cpuid4.l2_cache->share_level = MODULE; + } else { + error_setg(errp, + "x-l2-cache-topo doesn't support '%s', " + "and it only supports 'core' or 'cluster'", + cpu->l2_cache_topo_level); + return; + } + } + #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); qemu_register_reset(x86_cpu_machine_reset_cb, cpu); @@ -7135,6 +7165,7 @@ static Property x86_cpu_properties[] = { false), DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), + DEFINE_PROP_STRING("x-l2-cache-topo", X86CPU, l2_cache_topo_level), DEFINE_PROP_END_OF_LIST() }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5a955431f759..aa7e96c586c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1987,6 +1987,8 @@ struct ArchCPU { int32_t thread_id; int32_t hv_max_vps; + + char *l2_cache_topo_level; };