diff mbox series

[V2,06/10] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table

Message ID 20230213144038.2547584-7-sunilvl@ventanamicro.com (mailing list archive)
State New, archived
Headers show
Series Add basic ACPI support for risc-v virt | expand

Commit Message

Sunil V L Feb. 13, 2023, 2:40 p.m. UTC 
RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
Table (RHCT). Add this to the ACPI tables.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 hw/riscv/virt-acpi-build.c | 62 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

Comments

Andrew Jones Feb. 15, 2023, 1:22 p.m. UTC | #1 
On Mon, Feb 13, 2023 at 08:10:34PM +0530, Sunil V L wrote:
> RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
> Table (RHCT). Add this to the ACPI tables.
> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  hw/riscv/virt-acpi-build.c | 62 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index f54e3fb731..a2054f79a8 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -35,6 +35,7 @@
>  #include "hw/pci-host/gpex.h"
>  #include "qapi/error.h"
>  #include "migration/vmstate.h"
> +#include "hw/intc/riscv_aclint.h"
>  
>  #define ACPI_BUILD_TABLE_SIZE             0x20000
>  
> @@ -85,6 +86,67 @@ acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
>      aml_append(scope, dev);
>  }
>  
> +#define RHCT_NODE_ARRAY_OFFSET 56
> +static void
> +build_rhct(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
> +{
> +    MachineState *ms = MACHINE(s);
> +    uint32_t acpi_proc_id = 0;
> +    int i, socket;
> +    RISCVCPU *cpu;
> +    char *isa;
> +    size_t len, aligned_len;
> +    uint32_t isa_offset, num_rhct_nodes;
> +
> +    AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> +                        .oem_table_id = s->oem_table_id };
> +
> +    acpi_table_begin(&table, table_data);
> +
> +    build_append_int_noprefix(table_data, 0x0, 4);   /* Reserved */
> +    build_append_int_noprefix(table_data,
> +                              RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8);

Need "Time Base Frequency" comment.

> +
> +    /* ISA + N hart info */
> +    num_rhct_nodes = 1 + ms->smp.cpus;
> +    build_append_int_noprefix(table_data, num_rhct_nodes, 4);

/* Number of RHCT nodes */

> +    build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4);

/* Offset to the RHCT node array */

> +
> +    /* ISA string node */
> +    isa_offset = table_data->len - table.table_offset;
> +    build_append_int_noprefix(table_data, 0, 2);   /* Type 0*/
                                                               ^ need
							       space
> +
> +    cpu = &s->soc[0].harts[0];
> +    isa = riscv_isa_string(cpu);
> +    len = 8 + strlen(isa) + 1;
> +    aligned_len = (len % 2) ? (len + 1) : len;
> +
> +    build_append_int_noprefix(table_data, aligned_len, 2);   /* Total length */

s/Total length/Length/

> +    build_append_int_noprefix(table_data, 0x1, 2);           /* Revision */
> +
> +    /* ISA string length including NUL */

/* ISA Length including NUL */

> +    build_append_int_noprefix(table_data, strlen(isa) + 1, 2);
> +    g_array_append_vals(table_data, isa, strlen(isa) + 1);   /* ISA string */
> +
> +    if (aligned_len != len) {
> +        build_append_int_noprefix(table_data, 0x0, 1);   /* pad */

s/pad/Optional Padding/

> +    }
> +
> +    for (socket = 0; socket < riscv_socket_count(ms); socket++) {
> +        for (i = 0; i < s->soc[socket].num_harts; i++) {
> +            build_append_int_noprefix(table_data, 0xFFFF, 2);  /* Type */
> +            build_append_int_noprefix(table_data, 16, 2);      /* Length */
> +            build_append_int_noprefix(table_data, 0x1, 2);     /* Revision */
> +            build_append_int_noprefix(table_data, 1, 2); /* number of offsets */

s/number/Number/

> +            build_append_int_noprefix(table_data, acpi_proc_id, 4); /* UID */

ACPI Processor UID

> +            build_append_int_noprefix(table_data, isa_offset, 4);

/* Offsets */

> +            acpi_proc_id++;
> +        }
> +    }
> +
> +    acpi_table_end(linker, &table);
> +}
> +
>  /* FADT */
>  static void
>  build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
> -- 
> 2.34.1
>

Other than getting the comments to match the spec fields,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew
diff mbox series

Patch

diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index f54e3fb731..a2054f79a8 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -35,6 +35,7 @@ 
 #include "hw/pci-host/gpex.h"
 #include "qapi/error.h"
 #include "migration/vmstate.h"
+#include "hw/intc/riscv_aclint.h"
 
 #define ACPI_BUILD_TABLE_SIZE             0x20000
 
@@ -85,6 +86,67 @@  acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
     aml_append(scope, dev);
 }
 
+#define RHCT_NODE_ARRAY_OFFSET 56
+static void
+build_rhct(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
+{
+    MachineState *ms = MACHINE(s);
+    uint32_t acpi_proc_id = 0;
+    int i, socket;
+    RISCVCPU *cpu;
+    char *isa;
+    size_t len, aligned_len;
+    uint32_t isa_offset, num_rhct_nodes;
+
+    AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
+                        .oem_table_id = s->oem_table_id };
+
+    acpi_table_begin(&table, table_data);
+
+    build_append_int_noprefix(table_data, 0x0, 4);   /* Reserved */
+    build_append_int_noprefix(table_data,
+                              RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8);
+
+    /* ISA + N hart info */
+    num_rhct_nodes = 1 + ms->smp.cpus;
+    build_append_int_noprefix(table_data, num_rhct_nodes, 4);
+    build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4);
+
+    /* ISA string node */
+    isa_offset = table_data->len - table.table_offset;
+    build_append_int_noprefix(table_data, 0, 2);   /* Type 0*/
+
+    cpu = &s->soc[0].harts[0];
+    isa = riscv_isa_string(cpu);
+    len = 8 + strlen(isa) + 1;
+    aligned_len = (len % 2) ? (len + 1) : len;
+
+    build_append_int_noprefix(table_data, aligned_len, 2);   /* Total length */
+    build_append_int_noprefix(table_data, 0x1, 2);           /* Revision */
+
+    /* ISA string length including NUL */
+    build_append_int_noprefix(table_data, strlen(isa) + 1, 2);
+    g_array_append_vals(table_data, isa, strlen(isa) + 1);   /* ISA string */
+
+    if (aligned_len != len) {
+        build_append_int_noprefix(table_data, 0x0, 1);   /* pad */
+    }
+
+    for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+        for (i = 0; i < s->soc[socket].num_harts; i++) {
+            build_append_int_noprefix(table_data, 0xFFFF, 2);  /* Type */
+            build_append_int_noprefix(table_data, 16, 2);      /* Length */
+            build_append_int_noprefix(table_data, 0x1, 2);     /* Revision */
+            build_append_int_noprefix(table_data, 1, 2); /* number of offsets */
+            build_append_int_noprefix(table_data, acpi_proc_id, 4); /* UID */
+            build_append_int_noprefix(table_data, isa_offset, 4);
+            acpi_proc_id++;
+        }
+    }
+
+    acpi_table_end(linker, &table);
+}
+
 /* FADT */
 static void
 build_fadt_rev6(GArray *table_data, BIOSLinker *linker,