diff mbox series

[09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc

Message ID 20230214083833.44205-10-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series target/riscv: Some updates to float point related extensions | expand

Commit Message

Weiwei Li Feb. 14, 2023, 8:38 a.m. UTC 
Check for Zve32f/Zve64d can overlap check for F/D

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Daniel Henrique Barboza Feb. 14, 2023, 1:26 p.m. UTC | #1 
On 2/14/23 05:38, Weiwei Li wrote:
> Check for Zve32f/Zve64d can overlap check for F/D
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6f7ecf1a68..9b2711b94b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s)
>       switch (s->sew) {
>       case MO_16:
>       case MO_32:
> -        return has_ext(s, RVF);
> +        return s->cfg_ptr->ext_zve32f;
>       case MO_64:
> -        return has_ext(s, RVD);
> +        return s->cfg_ptr->ext_zve64d;
>       default:
>           return false;
>       }
> @@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s)
>       switch (s->sew) {
>       case MO_8:
>       case MO_16:
> -        return has_ext(s, RVF);
> +        return s->cfg_ptr->ext_zve32f;
>       case MO_32:
> -        return has_ext(s, RVD);
> +        return s->cfg_ptr->ext_zve64d;
>       default:
>           return false;
>       }
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6f7ecf1a68..9b2711b94b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -41,9 +41,9 @@  static bool require_rvf(DisasContext *s)
     switch (s->sew) {
     case MO_16:
     case MO_32:
-        return has_ext(s, RVF);
+        return s->cfg_ptr->ext_zve32f;
     case MO_64:
-        return has_ext(s, RVD);
+        return s->cfg_ptr->ext_zve64d;
     default:
         return false;
     }
@@ -58,9 +58,9 @@  static bool require_scale_rvf(DisasContext *s)
     switch (s->sew) {
     case MO_8:
     case MO_16:
-        return has_ext(s, RVF);
+        return s->cfg_ptr->ext_zve32f;
     case MO_32:
-        return has_ext(s, RVD);
+        return s->cfg_ptr->ext_zve64d;
     default:
         return false;
     }