| Message ID | 20230214083833.44205-2-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Some updates to float point related extensions | expand |
On 2/14/23 05:38, Weiwei Li wrote: > Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0dd2f0c753..eb0cd12a6a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -729,7 +729,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { > + if (cpu->cfg.ext_zfh) { > + cpu->cfg.ext_zfhmin = true; > + } > + > + if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { > error_setg(errp, "Zfh/Zfhmin extensions require F extension"); > return; > }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dd2f0c753..eb0cd12a6a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -729,7 +729,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zfh) { + cpu->cfg.ext_zfhmin = true; + } + + if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; }