From patchwork Thu Feb 16 16:21:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13143457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D03B4C61DA4 for ; Thu, 16 Feb 2023 16:22:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pSh0z-00006A-IT; Thu, 16 Feb 2023 11:21:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pSh0y-0008VW-DN for qemu-devel@nongnu.org; Thu, 16 Feb 2023 11:21:44 -0500 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pSh0w-0005um-Hv for qemu-devel@nongnu.org; Thu, 16 Feb 2023 11:21:44 -0500 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-16346330067so3125965fac.3 for ; Thu, 16 Feb 2023 08:21:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zeLc19rvg9BNm7u7QZh1b1577pYy8eBeQfNkS++7q68=; b=SLksprB9WShuzZA1//4KSOM0lCFgf5VqXYZZfXe83kxhlNb5IbjbP947ABVXvNNnEg WzcWpDLWcDqoCA+Yra+xS9cRDyVBDgvJ5Td0DLT/9kHLDPOHipNTw5TPcuWibwQpNElb dIF1tSwcCMnTlCImYF1Hjr18ou+svLeWowGA7JkpWQx6aUeK12DC9qcLf7m1gcpt3IHB aIg3u4txnq7GoYeo2eodFjmm+DfdAGiISLjSDV8p/IWWOyiy3496FY40q/jerN6tNKyT veShCyrWrJSCJGUMXZ1JiJtmygI5NsedTjI4DGzMFoleqELCMd92cN17N6LTk65R+y9Y ARSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zeLc19rvg9BNm7u7QZh1b1577pYy8eBeQfNkS++7q68=; b=t5G3JJOh51XIERprBQ+/WNQzZw8I+KoEotK+lmwd6dcNQ/xCaJZ+iO8pKiRdw6jc+K J219BsblvnCU5X4l3WpOKofNYtcM2Hqz8zctHOylWbJBEgz7UyLPf7TZ5qMmLXkMf1ol MnStX8Qg1/ZQM6vQbGgRC5kQTm7Cv16XHTxTEGZpgs5ZawDSkkIQPfnCLPWPL0ohqt5m wYCEcvwekhxXLTy6kdH68PGpvAuLjjRtZv1gaRpVW1/G6Vd28a4F2MijS34m46hc27nz 6JrhTswqsq5E4TdK8VZiTCBcqb52+HSRL5Rez3qHBavzkHY5XLKpP1h5k4KHwRXL3Fqz IkVg== X-Gm-Message-State: AO0yUKXhY3xSjJ1Xaf0gG4kMKK8ItRhOcHEwT5eDSoaie/OWyvZy8SMK eb9q/Ok4CrYksaRvrS78D48WHuBSKbCywDO3 X-Google-Smtp-Source: AK7set95ceZoASd8qsGKLKrv6PKnHuOyLvKE0Ro6kG5oblULH7R7AbMUbvTHWw8iWz3bb/qICvII5g== X-Received: by 2002:a05:6870:82ac:b0:16d:e6f9:c20f with SMTP id q44-20020a05687082ac00b0016de6f9c20fmr3678168oae.54.1676564501500; Thu, 16 Feb 2023 08:21:41 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.19.40.109]) by smtp.gmail.com with ESMTPSA id z17-20020a056870e15100b001600797d1b5sm693029oaa.41.2023.02.16.08.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 08:21:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v5 3/9] target/riscv: remove RISCV_FEATURE_DEBUG Date: Thu, 16 Feb 2023 13:21:20 -0300 Message-Id: <20230216162126.809482-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230216162126.809482-1-dbarboza@ventanamicro.com> References: <20230216162126.809482-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 6 +----- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 3 +-- 5 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93b52b826c..e34a5e3f11 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (cpu->cfg.debug) { riscv_trigger_init(env); } @@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.debug) { - riscv_set_feature(env, RISCV_FEATURE_DEBUG); - } - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 368a522b5b..7326aaed27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_DEBUG }; /* Privileged specification version */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ad8d82662c..4cdd247c6c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } - if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f7862ff4a4..90dc28e22e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno) static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (riscv_cpu_cfg(env).debug) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c6ce318cce..4634968898 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = { static bool debug_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_feature(env, RISCV_FEATURE_DEBUG); + return cpu->cfg.debug; } static int debug_post_load(void *opaque, int version_id)