From patchwork Fri Feb 17 17:51:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 13145102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F256FC05027 for ; Fri, 17 Feb 2023 17:55:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pT4vV-0005Am-C8; Fri, 17 Feb 2023 12:53:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pT4vT-000593-75 for qemu-devel@nongnu.org; Fri, 17 Feb 2023 12:53:39 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pT4vR-0000tB-CR for qemu-devel@nongnu.org; Fri, 17 Feb 2023 12:53:38 -0500 Received: by mail-pj1-x1033.google.com with SMTP id s4-20020a17090a764400b002349a303ca5so2068361pjl.4 for ; Fri, 17 Feb 2023 09:53:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=to:from:cc:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:from:to:cc:subject:date :message-id:reply-to; bh=j3hxgJioJYDaoMVQqM2mg2oa252Bx0zdrz7vXWPM9MA=; b=7HWdanCB8vxeAxFHcV5Cb5q3+S35sI6cnLnFnG00qxHIC+zakD8qI32WfzgbDyghpD Q6B4vhaFIWmSGTcwW09ybSgRmXoNQI3AVYG3O35uHPi1kpkUqR55RI6Sd98fFZSP3B73 mXSV3BvBuNRn8dofljP4V8wnnOUjbAvr6Yy4ZaGqAhAG+Xtnx7FMFtd7AnF6jYoTGhA0 kIO2ssmESJhlyL+S8ywMSHXuEFkEW9ELvTf2A6N5LriZXZsntqZyuVW9bM1zW2+b7J8K uKY2x7DVIVLfH4CNf1oILhutcr2lrLUpM2YMUhBPLG6qoM3ffxxipvJWcuW1WTYGLCIr 6H/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:from:cc:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j3hxgJioJYDaoMVQqM2mg2oa252Bx0zdrz7vXWPM9MA=; b=2S5ZGibP/Tumi1lYm1ydhwhG6lxQHVmYgMCXaab0m+fvCZj4t/KojWGI1VZAW5YhoF JpBhDc1hNGbP8IONuhBa9nY/CcU0uCZHCU5CQj0CoT1FsISgzY5gfGRJFe7w9GiAOSdJ nOHJxzNZeLVWL7zdLhEjuLqh6NP5Id1b4DPcnUAbchhsH4+XDNmfIfyJbmPyg5vByWuX s2v+o9YklpBtMz9VxKXfa58t543igEpsFi5pTOQmOwcmT3B/L3/p6kTKGkAnKRTklbK3 quYSu7N39tMThrhvJ+6Oleii21+crU8o/3FC/Wl0DF/096gNpIHaJL2DMrHhhmSBFEy/ jUHQ== X-Gm-Message-State: AO0yUKWbvxWiEyujjJ/0xfoOEZumssfNGVG1xNUeJIVjowc21AnYMgmi EB2VjA66fYWoUKQ9MhQR/krnSQ== X-Google-Smtp-Source: AK7set+g2zKwdoruljwUYqbyQiss/0bDeBRHMDD6NAToHApUIyO1itl/67FLgJD6u7hafNO+wNsIiA== X-Received: by 2002:a17:902:d4cd:b0:19a:b033:2bb0 with SMTP id o13-20020a170902d4cd00b0019ab0332bb0mr192870plg.46.1676656415232; Fri, 17 Feb 2023 09:53:35 -0800 (PST) Received: from localhost ([135.180.226.51]) by smtp.gmail.com with ESMTPSA id jc11-20020a17090325cb00b0019607547f29sm3392166plb.304.2023.02.17.09.53.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 09:53:34 -0800 (PST) Subject: [PULL 3/9] hw/riscv/boot.c: make riscv_load_initrd() static Date: Fri, 17 Feb 2023 09:51:57 -0800 Message-Id: <20230217175203.19510-4-palmer@rivosinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230217175203.19510-1-palmer@rivosinc.com> References: <20230217175203.19510-1-palmer@rivosinc.com> MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Daniel Henrique Barboza , ilippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Alistair Francis , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=palmer@rivosinc.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20230206140022.2748401-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4954bb9d4b..52bf8e67de 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename != NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong kernel_start_addr, @@ -234,46 +274,6 @@ out: return kernel_entry; } -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename != NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - /* * This function makes an assumption that the DRAM interval * 'dram_base' + 'dram_size' is contiguous. diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index ea1de8b020..a2e4ae9cb0 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,7 +48,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, MachineState *ms); void riscv_load_fdt(hwaddr fdt_addr, void *fdt);