From patchwork Fri Feb 24 18:59:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 13151699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42ACEC7EE23 for ; Fri, 24 Feb 2023 19:03:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pVdJn-0001iW-AQ; Fri, 24 Feb 2023 14:01:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pVdJk-0001gI-N9 for qemu-devel@nongnu.org; Fri, 24 Feb 2023 14:01:16 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pVdJd-0002eH-NW for qemu-devel@nongnu.org; Fri, 24 Feb 2023 14:01:16 -0500 Received: by mail-pj1-x102b.google.com with SMTP id c23so24877pjo.4 for ; Fri, 24 Feb 2023 11:01:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1677265265; h=to:from:cc:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:from:to:cc:subject:date :message-id:reply-to; bh=DDWoUrS3gNFU9IU+ndidQqS1Eb6eRflzx7e/dFgHmuQ=; b=IAaDUpJhI0v5JUSkQW4z8WzozeBheiRWzFaJ0QqmwvGt2zr0R6sB4BmJ+cu+ur6cGq ZUOO2xL7Stru3W8DTDpQxYTjrjMXFmPMhYTN8Wv9S+XX8/rixGQFEj39eWV9QwUaH/Q5 sFBVkDlTbqUGWVGWDEJnAJIPzmBS3sk3pODkk2upcFVxkv2QjkGauxy+YwX6JwwGu0I1 9uYULWpDxkYMvlOBNjaK0EZlv6C9IgAJ+CkneHaDTUbCqYFiXaL2nuIlodiv9kz2Q2MK 0gYz0cWbqZfSLeA8OsmD90YR9ZWGPo8WG6FddbOXVZKDT4nyNze68WnOIqn46VlSV1DA dTHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677265265; h=to:from:cc:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DDWoUrS3gNFU9IU+ndidQqS1Eb6eRflzx7e/dFgHmuQ=; b=MnIwhMdSwwLM7CeIRVdItoxldKWBCZkAzEJMfnmxL8Dp/I4HdX+D1TX9nvVMWJyAA7 sqFfsDvKyjVSn+/K7TUoMCSCojyf2UIGmFyopRgnBCA/EyTRyBdLXVFVQNRECXBimeHZ n6gM43sS+CMELYe2CtKKH6l4eFr3RraJJYrmvbz0CMh00d75+4VfMTPwUN8+H1drv1b+ Z+wSxKvc2EPB+pkcCDi7UHMU9eorn9UfAAm2oMqUGjpYpwPaym26Zpji0zlpLFE88/HH Lpwm4TgTpio+ttJWiTgNrf+m8Na1PVLoqHKGd2NcPzjilcUn/NJ0xTL3BNJlTG3/wUzT NFpQ== X-Gm-Message-State: AO0yUKX+nWBB8WTWdBx9sHWGD4jYpZIMhud2zfRK0pePOZCZfw84DMxK NFSuYc7yCrtH5DYv6B2pfPYc7w== X-Google-Smtp-Source: AK7set+WZgU+3zTTjYykNv3PGxEC8vR7LqK29oW2oCpdeTYLLRkbsX8n0RfYO94RsoPS1UUCKoxG7Q== X-Received: by 2002:a17:902:e74f:b0:199:2e77:fe56 with SMTP id p15-20020a170902e74f00b001992e77fe56mr21524320plf.52.1677265264643; Fri, 24 Feb 2023 11:01:04 -0800 (PST) Received: from localhost ([135.180.224.71]) by smtp.gmail.com with ESMTPSA id g5-20020a170902c38500b0019c92f56983sm7512159plg.120.2023.02.24.11.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 11:01:04 -0800 (PST) Subject: [PULL 4/8] target/riscv: Remove privileged spec version restriction for RVV Date: Fri, 24 Feb 2023 10:59:05 -0800 Message-Id: <20230224185908.32706-5-palmer@rivosinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230224185908.32706-1-palmer@rivosinc.com> References: <20230224185908.32706-1-palmer@rivosinc.com> MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Frank Chang , Bin Meng , LIU Zhiwei , Alistair Francis , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=palmer@rivosinc.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frank Chang The RVV specification does not require that the core needs to support the privileged specification v1.12.0 to support RVV, and there is no dependency from ISA level. This commit removes the restriction from both RVV CSRs and extension CPU ISA string. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Reviewed-by: LIU Zhiwei Acked-by: Alistair Francis Message-Id: <20230208063209.27279-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/csr.c | 21 +++++++-------------- 2 files changed, 8 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dd2f0c753..93b52b826c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -73,7 +73,7 @@ struct isa_ext_data { */ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), - ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), + ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fa17d7770c..1b0a0c1693 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3980,20 +3980,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_FRM] = { "frm", fs, read_frm, write_frm }, [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VL] = { "vl", vs, read_vl, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VTYPE] = { "vtype", vs, read_vtype, - .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_VLENB] = { "vlenb", vs, read_vlenb, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, + [CSR_VL] = { "vl", vs, read_vl }, + [CSR_VTYPE] = { "vtype", vs, read_vtype }, + [CSR_VLENB] = { "vlenb", vs, read_vlenb }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, [CSR_INSTRET] = { "instret", ctr, read_hpmcounter },