| Message ID | 20230227135202.9710-18-anjo@rev.ng (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Replace TARGET_TB_PCREL with CF_PCREL | expand |
On Mon, 27 Feb 2023 05:51:52 PST (-0800), anjo@rev.ng wrote: > Signed-off-by: Anton Johansson <anjo@rev.ng> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/riscv/cpu.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 93b52b826c..9eb748a283 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -34,6 +34,7 @@ > #include "fpu/softfloat-helpers.h" > #include "sysemu/kvm.h" > #include "kvm_riscv.h" > +#include "tcg/tcg.h" > > /* RISC-V CPU definitions */ > > @@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, > CPURISCVState *env = &cpu->env; > RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); > > + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); > + > if (xl == MXL_RV32) { > - env->pc = (int32_t)tb_pc(tb); > + env->pc = (int32_t) tb->pc; > } else { > - env->pc = tb_pc(tb); > + env->pc = tb->pc; > } > } Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Thanks! I'm going to assume you want these to stay together, but LMK if you were looking to aim this at the RISC-V tree.
On 2/27/23 13:05, Palmer Dabbelt wrote: > On Mon, 27 Feb 2023 05:51:52 PST (-0800), anjo@rev.ng wrote: >> Signed-off-by: Anton Johansson <anjo@rev.ng> >> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> target/riscv/cpu.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 93b52b826c..9eb748a283 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -34,6 +34,7 @@ >> #include "fpu/softfloat-helpers.h" >> #include "sysemu/kvm.h" >> #include "kvm_riscv.h" >> +#include "tcg/tcg.h" >> >> /* RISC-V CPU definitions */ >> >> @@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, >> CPURISCVState *env = &cpu->env; >> RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); >> >> + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); >> + >> if (xl == MXL_RV32) { >> - env->pc = (int32_t)tb_pc(tb); >> + env->pc = (int32_t) tb->pc; >> } else { >> - env->pc = tb_pc(tb); >> + env->pc = tb->pc; >> } >> } > > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > Thanks! I'm going to assume you want these to stay together, but LMK if you were looking > to aim this at the RISC-V tree. I've queued to tcg-next, so they'll stay together. I've now added your r-b. r~
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93b52b826c..9eb748a283 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,7 @@ #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" #include "kvm_riscv.h" +#include "tcg/tcg.h" /* RISC-V CPU definitions */ @@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, CPURISCVState *env = &cpu->env; RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + if (xl == MXL_RV32) { - env->pc = (int32_t)tb_pc(tb); + env->pc = (int32_t) tb->pc; } else { - env->pc = tb_pc(tb); + env->pc = tb->pc; } }