| Message ID | 20230228093619.342575-1-eric.auger@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] target/arm: Add raw_writes ops for register whose write induce TLB maintenance | expand |
Hi Peter, On 2/28/23 10:36, Eric Auger wrote: > Some registers whose 'cooked' writefns induce TLB maintenance do > not have raw_writefn ops defined. If only the writefn ops is set > (ie. no raw_writefn is provided), it is assumed the cooked also > work as the raw one. For those registers it is not obvious the > tlb_flush works on KVM mode so better/safer setting the raw write. > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > Suggested-by: Peter Maydell <peter.maydell@linaro.org> If I am not wrong this patch fell into the cracks. Is it in a decent state now? Thanks Eric > > --- > > v2 -> v3: > - remove modifs related to ARM_CP_NO_RAW regs [Peter] > - do not add raw_writefn for hcr_writelow and hcr_writehigh > > v1 -> v2: > - do not add raw_writefn if type is set to ARM_CP_NO_RAW [Peter] > --- > target/arm/helper.c | 23 +++++++++++++---------- > 1 file changed, 13 insertions(+), 10 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 14af7ba095..42ada408cc 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -4184,14 +4184,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { > .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, > .access = PL1_RW, .accessfn = access_tvm_trvm, > .fgt = FGT_TTBR0_EL1, > - .writefn = vmsa_ttbr_write, .resetvalue = 0, > + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, > .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), > offsetof(CPUARMState, cp15.ttbr0_ns) } }, > { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, > .access = PL1_RW, .accessfn = access_tvm_trvm, > .fgt = FGT_TTBR1_EL1, > - .writefn = vmsa_ttbr_write, .resetvalue = 0, > + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, > .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), > offsetof(CPUARMState, cp15.ttbr1_ns) } }, > { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, > @@ -4451,13 +4451,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { > .type = ARM_CP_64BIT | ARM_CP_ALIAS, > .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), > offsetof(CPUARMState, cp15.ttbr0_ns) }, > - .writefn = vmsa_ttbr_write, }, > + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, > { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, > .access = PL1_RW, .accessfn = access_tvm_trvm, > .type = ARM_CP_64BIT | ARM_CP_ALIAS, > .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), > offsetof(CPUARMState, cp15.ttbr1_ns) }, > - .writefn = vmsa_ttbr_write, }, > + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, > }; > > static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) > @@ -5900,7 +5900,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .type = ARM_CP_IO, > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), > - .writefn = hcr_write }, > + .writefn = hcr_write, .raw_writefn = raw_write }, > { .name = "HCR", .state = ARM_CP_STATE_AA32, > .type = ARM_CP_ALIAS | ARM_CP_IO, > .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > @@ -5972,6 +5972,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, > .access = PL2_RW, .writefn = vmsa_tcr_el12_write, > + .raw_writefn = raw_write, > .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, > { .name = "VTCR", .state = ARM_CP_STATE_AA32, > .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, > @@ -5988,10 +5989,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .type = ARM_CP_64BIT | ARM_CP_ALIAS, > .access = PL2_RW, .accessfn = access_el3_aa32ns, > .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), > - .writefn = vttbr_write }, > + .writefn = vttbr_write, .raw_writefn = raw_write }, > { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, > - .access = PL2_RW, .writefn = vttbr_write, > + .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, > .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, > { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, > @@ -6003,7 +6004,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, > { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, > - .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, > + .access = PL2_RW, .resetvalue = 0, > + .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, > .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, > { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, > .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, > @@ -6190,12 +6192,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { > { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), > - .resetfn = scr_reset, .writefn = scr_write }, > + .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write }, > { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, > .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, > .access = PL1_RW, .accessfn = access_trap_aa32s_el1, > .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), > - .writefn = scr_write }, > + .writefn = scr_write, .raw_writefn = raw_write }, > { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, > .access = PL3_RW, .resetvalue = 0, > @@ -7839,6 +7841,7 @@ static const ARMCPRegInfo vhe_reginfo[] = { > { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, > .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, > + .raw_writefn = raw_write, > .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, > #ifndef CONFIG_USER_ONLY > { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
On Fri, 23 Jun 2023 at 17:43, Eric Auger <eric.auger@redhat.com> wrote: > > Hi Peter, > > On 2/28/23 10:36, Eric Auger wrote: > > Some registers whose 'cooked' writefns induce TLB maintenance do > > not have raw_writefn ops defined. If only the writefn ops is set > > (ie. no raw_writefn is provided), it is assumed the cooked also > > work as the raw one. For those registers it is not obvious the > > tlb_flush works on KVM mode so better/safer setting the raw write. > > > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > > Suggested-by: Peter Maydell <peter.maydell@linaro.org> > > If I am not wrong this patch fell into the cracks. Is it in a decent > state now? Oops, sorry about that. Yes, I think v3 looks good; I've applied it to target-arm.next. thanks -- PMM
Hi Peter, On 6/27/23 14:23, Peter Maydell wrote: > On Fri, 23 Jun 2023 at 17:43, Eric Auger <eric.auger@redhat.com> wrote: >> Hi Peter, >> >> On 2/28/23 10:36, Eric Auger wrote: >>> Some registers whose 'cooked' writefns induce TLB maintenance do >>> not have raw_writefn ops defined. If only the writefn ops is set >>> (ie. no raw_writefn is provided), it is assumed the cooked also >>> work as the raw one. For those registers it is not obvious the >>> tlb_flush works on KVM mode so better/safer setting the raw write. >>> >>> Signed-off-by: Eric Auger <eric.auger@redhat.com> >>> Suggested-by: Peter Maydell <peter.maydell@linaro.org> >> If I am not wrong this patch fell into the cracks. Is it in a decent >> state now? > Oops, sorry about that. Yes, I think v3 looks good; I've > applied it to target-arm.next. no problem. thanks! Eric > > thanks > -- PMM >
diff --git a/target/arm/helper.c b/target/arm/helper.c index 14af7ba095..42ada408cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4184,14 +4184,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR0_EL1, - .writefn = vmsa_ttbr_write, .resetvalue = 0, + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR1_EL1, - .writefn = vmsa_ttbr_write, .resetvalue = 0, + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, @@ -4451,13 +4451,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, }; static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5900,7 +5900,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_write }, + .writefn = hcr_write, .raw_writefn = raw_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, @@ -5972,6 +5972,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .writefn = vmsa_tcr_el12_write, + .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name = "VTCR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, @@ -5988,10 +5989,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .type = ARM_CP_64BIT | ARM_CP_ALIAS, .access = PL2_RW, .accessfn = access_el3_aa32ns, .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), - .writefn = vttbr_write }, + .writefn = vttbr_write, .raw_writefn = raw_write }, { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, - .access = PL2_RW, .writefn = vttbr_write, + .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, @@ -6003,7 +6004,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, + .access = PL2_RW, .resetvalue = 0, + .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6190,12 +6192,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .resetfn = scr_reset, .writefn = scr_write }, + .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write }, { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_trap_aa32s_el1, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn = scr_write }, + .writefn = scr_write, .raw_writefn = raw_write }, { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, .access = PL3_RW, .resetvalue = 0, @@ -7839,6 +7841,7 @@ static const ARMCPRegInfo vhe_reginfo[] = { { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, + .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, #ifndef CONFIG_USER_ONLY { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
Some registers whose 'cooked' writefns induce TLB maintenance do not have raw_writefn ops defined. If only the writefn ops is set (ie. no raw_writefn is provided), it is assumed the cooked also work as the raw one. For those registers it is not obvious the tlb_flush works on KVM mode so better/safer setting the raw write. Signed-off-by: Eric Auger <eric.auger@redhat.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> --- v2 -> v3: - remove modifs related to ARM_CP_NO_RAW regs [Peter] - do not add raw_writefn for hcr_writelow and hcr_writehigh v1 -> v2: - do not add raw_writefn if type is set to ARM_CP_NO_RAW [Peter] --- target/arm/helper.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-)