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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id j2-20020a170902758200b0019b06263bcasm1556896pll.247.2023.02.28.05.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 05:45:43 -0800 (PST) From: Bin Meng To: qemu-devel@nongnu.org Cc: Bin Meng , Weiwei Li , LIU Zhiwei , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs Date: Tue, 28 Feb 2023 21:45:30 +0800 Message-Id: <20230228104035.1879882-14-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228104035.1879882-1-bmeng@tinylab.org> References: <20230228104035.1879882-13-bmeng@tinylab.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bin Meng At present user timer and counter CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by adding a debugger check in their predicate() routine. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- (no changes since v1) target/riscv/csr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7284fd8a0d..10ae5df5e6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -131,6 +131,10 @@ static RISCVException ctr(CPURISCVState *env, int csrno) skip_ext_pmu_check: + if (env->debugger) { + return RISCV_EXCP_NONE; + } + if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) { return RISCV_EXCP_ILLEGAL_INST; }