| Message ID | 20230303083740.12817-1-palmer@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 3 Mar 2023 at 08:41, Palmer Dabbelt <palmer@rivosinc.com> wrote: > > merged tag 'buildsys-qom-qdev-ui-20230227' > The following changes since commit 627634031092e1514f363fd8659a579398de0f0e: > > Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging (2023-02-28 15:09:18 +0000) > > are available in the Git repository at: > > https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230303 > > for you to fetch changes up to 37151032989ecf6e7ce8b65bc7bcb400d0318b2c: > > Merge patch series "target/riscv: some vector_helper.c cleanups" (2023-03-01 18:09:48 -0800) > > ---------------------------------------------------------------- > Fifth RISC-V PR for QEMU 8.0 > > * Experimantal support for writable misa. > * Support for Svadu extension. > * Support for the Zicond extension. > * Fixes to gdbstub, CSR accesses, dependencies between the various > floating-point exceptions, and XTheadMemPair. > * Many cleanups. > > ---------------------------------------------------------------- > There's a lot of cleanups here, a handful of which ended up stepping on > each other and were necessary for various features. I tried to keep > each individual patch set intact, but that led to some merge conflicts > and a bit of a clunky history -- I'm not sure what the right answer is > there, happy to re-spin this to be more linear if that's problem for > folks. It looks like in this case you got lucky, but in general I don't recommend including merge commits in your pull requests, rather than fixing up patches by rebasing them. If I find that a pull request has merge conflicts when I try to merge it, I'm going to kick it back to you to rebase, and then you need to rebase and fix up the commits in it anyway... thanks -- PMM
On Fri, 3 Mar 2023 at 08:41, Palmer Dabbelt <palmer@rivosinc.com> wrote: > > merged tag 'buildsys-qom-qdev-ui-20230227' > The following changes since commit 627634031092e1514f363fd8659a579398de0f0e: > > Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging (2023-02-28 15:09:18 +0000) > > are available in the Git repository at: > > https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230303 > > for you to fetch changes up to 37151032989ecf6e7ce8b65bc7bcb400d0318b2c: > > Merge patch series "target/riscv: some vector_helper.c cleanups" (2023-03-01 18:09:48 -0800) > > ---------------------------------------------------------------- > Fifth RISC-V PR for QEMU 8.0 > > * Experimantal support for writable misa. > * Support for Svadu extension. > * Support for the Zicond extension. > * Fixes to gdbstub, CSR accesses, dependencies between the various > floating-point exceptions, and XTheadMemPair. > * Many cleanups. > > ---------------------------------------------------------------- > There's a lot of cleanups here, a handful of which ended up stepping on > each other and were necessary for various features. I tried to keep > each individual patch set intact, but that led to some merge conflicts > and a bit of a clunky history -- I'm not sure what the right answer is > there, happy to re-spin this to be more linear if that's problem for > folks. > > Unfortunately the OpenSBI bump is still failing CI, it turns out I > missed the second stage. I was intending on having a sixth PR anyway as > I'd really like to get the ACPI patches in for 8.0 so we can start > testing everywhere else. There's also a patch set from Daniel that's > ready to go but depends on some recently merged TCG patches, so I > figured it'd be better to just send what's ready now rather than trying > to make the history more complicated. > > This all passes my local tests ("make check" and a bunch of Linux > configs), but "push-ci-now" is still tripping up on OpenSBI as that's > due to some network resources changing. With any luck I'll have some > time to sort things out this weekend (though always happy to have some > help if anyone wants to throw in some time). > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM
merged tag 'buildsys-qom-qdev-ui-20230227' The following changes since commit 627634031092e1514f363fd8659a579398de0f0e: Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging (2023-02-28 15:09:18 +0000) are available in the Git repository at: https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230303 for you to fetch changes up to 37151032989ecf6e7ce8b65bc7bcb400d0318b2c: Merge patch series "target/riscv: some vector_helper.c cleanups" (2023-03-01 18:09:48 -0800) ---------------------------------------------------------------- Fifth RISC-V PR for QEMU 8.0 * Experimantal support for writable misa. * Support for Svadu extension. * Support for the Zicond extension. * Fixes to gdbstub, CSR accesses, dependencies between the various floating-point exceptions, and XTheadMemPair. * Many cleanups. ---------------------------------------------------------------- There's a lot of cleanups here, a handful of which ended up stepping on each other and were necessary for various features. I tried to keep each individual patch set intact, but that led to some merge conflicts and a bit of a clunky history -- I'm not sure what the right answer is there, happy to re-spin this to be more linear if that's problem for folks. Unfortunately the OpenSBI bump is still failing CI, it turns out I missed the second stage. I was intending on having a sixth PR anyway as I'd really like to get the ACPI patches in for 8.0 so we can start testing everywhere else. There's also a patch set from Daniel that's ready to go but depends on some recently merged TCG patches, so I figured it'd be better to just send what's ready now rather than trying to make the history more complicated. This all passes my local tests ("make check" and a bunch of Linux configs), but "push-ci-now" is still tripping up on OpenSBI as that's due to some network resources changing. With any luck I'll have some time to sort things out this weekend (though always happy to have some help if anyone wants to throw in some time). ---------------------------------------------------------------- Bin Meng (20): target/riscv: gdbstub: Check priv spec version before reporting CSR target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() target/riscv: Use g_assert() for the predicate() NULL check target/riscv: gdbstub: Minor change for better readability target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled target/riscv: Coding style fixes in csr.c target/riscv: Use 'bool' type for read_only target/riscv: Simplify {read, write}_pmpcfg() a little bit target/riscv: Simplify getting RISCVCPU pointer from env target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml target/riscv: Allow debugger to access user timer and counter CSRs target/riscv: Allow debugger to access seed CSR target/riscv: Allow debugger to access {h, s}stateen CSRs target/riscv: Allow debugger to access sstc CSRs target/riscv: Drop priv level check in mseccfg predicate() target/riscv: Group all predicate() routines together hw/riscv: Skip re-generating DT nodes for a given DTB hw/riscv: Move the dtb load bits outside of create_fdt() Christoph Müllner (1): RISC-V: XTheadMemPair: Remove register restrictions for store-pair Daniel Henrique Barboza (16): target/riscv: introduce riscv_cpu_cfg() target/riscv: do not mask unsupported QEMU extensions in write_misa() target/riscv: allow MISA writes as experimental target/riscv: remove RISCV_FEATURE_DEBUG target/riscv/cpu.c: error out if EPMP is enabled without PMP target/riscv: remove RISCV_FEATURE_EPMP target/riscv: remove RISCV_FEATURE_PMP hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() target/riscv: remove RISCV_FEATURE_MMU target/riscv/cpu: remove CPUArchState::features and friends target/riscv/csr.c: use env_archcpu() in ctr() target/riscv/csr.c: simplify mctr() target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig target/riscv/vector_helper.c: create vext_set_tail_elems_1s() target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig Palmer Dabbelt (6): Merge patch series "make write_misa a no-op and FEATURE_* cleanups" Merge patch series "target/riscv: Some updates to float point related extensions" Merge patch series "target/riscv: Various fixes to gdbstub and CSR access" Merge patch series "target/riscv: Add support for Svadu extension" Merge patch series "RISCVCPUConfig related cleanups" Merge patch series "target/riscv: some vector_helper.c cleanups" Shaobo Song (1): target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages Weiwei Li (21): target/riscv: Fix the relationship between Zfhmin and Zfh target/riscv: Fix the relationship between Zhinxmin and Zhinx target/riscv: Simplify the check for Zfhmin and Zhinxmin target/riscv: Add cfg properties for Zv* extensions target/riscv: Fix relationship between V, Zve*, F and D target/riscv: Add property check for Zvfh{min} extensions target/riscv: Indent fixes in cpu.c target/riscv: Simplify check for Zve32f and Zve64f target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc target/riscv: Remove redundunt check for zve32f and zve64f target/riscv: Add support for Zvfh/zvfhmin extensions target/riscv: Fix check for vector load/store instructions when EEW=64 target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc target/riscv: Expose properties for Zv* extensions target/riscv: Add support for Zicond extension target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg target/riscv: Add csr support for svadu target/riscv: Add *envcfg.PBMTE related check in address translation target/riscv: Add *envcfg.HADE related check in address translation target/riscv: Export Svadu property hw/riscv/sifive_u.c | 30 +-- hw/riscv/virt.c | 35 +-- include/hw/riscv/sifive_u.h | 1 + target/riscv/cpu.c | 134 ++++++---- target/riscv/cpu.h | 34 +-- target/riscv/cpu_bits.h | 4 + target/riscv/cpu_helper.c | 24 +- target/riscv/csr.c | 354 ++++++++++++++------------- target/riscv/gdbstub.c | 100 ++------ target/riscv/insn32.decode | 4 + target/riscv/insn_trans/trans_rvv.c.inc | 184 +++++--------- target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +- target/riscv/insn_trans/trans_rvzicond.c.inc | 49 ++++ target/riscv/insn_trans/trans_xthead.c.inc | 4 - target/riscv/machine.c | 11 +- target/riscv/monitor.c | 2 +- target/riscv/op_helper.c | 2 +- target/riscv/pmp.c | 8 +- target/riscv/translate.c | 3 +- target/riscv/vector_helper.c | 104 +++----- 20 files changed, 538 insertions(+), 574 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzicond.c.inc