Message ID | 20230303083740.12817-39-palmer@rivosinc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Series |
[PULL,01/59] target/riscv: introduce riscv_cpu_cfg()
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diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 10ae5df5e6..15b23b9b5a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -459,6 +459,10 @@ static RISCVException seed(CPURISCVState *env, int csrno) } #if !defined(CONFIG_USER_ONLY) + if (env->debugger) { + return RISCV_EXCP_NONE; + } + /* * With a CSR read-write instruction: * 1) The seed CSR is always available in machine mode as normal.