diff mbox series

[PULL,09/17] Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed

Message ID 20230307053438.2416629-10-tsimpson@quicinc.com (mailing list archive)
State New, archived
Headers show
Series [PULL,01/17] Hexagon (target/hexagon) Restore --disable-hexagon-idef-parser build | expand

Commit Message

Taylor Simpson March 7, 2023, 5:34 a.m. UTC 
The pkt_has_store_s1 field in CPUHexagonState is only needed in generated
helpers for scalar load instructions.  See check_noshuf and mem_load[1248]
in op_helper.c.

We add logic in gen_analyze_funcs.py to set need_pkt_has_store_s1 in
DisasContext when it is needed at runtime.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-7-tsimpson@quicinc.com>
---
 target/hexagon/translate.h          | 1 +
 target/hexagon/attribs_def.h.inc    | 1 +
 target/hexagon/translate.c          | 6 +++++-
 target/hexagon/gen_analyze_funcs.py | 5 +++++
 target/hexagon/hex_common.py        | 1 +
 5 files changed, 13 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index d45d3a4bb0..34368b2186 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -61,6 +61,7 @@  typedef struct DisasContext {
     TCGCond branch_cond;
     target_ulong branch_dest;
     bool is_tight_loop;
+    bool need_pkt_has_store_s1;
 } DisasContext;
 
 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 5d2a102c18..9874d1658f 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -44,6 +44,7 @@  DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "")
 DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "")
 DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "")
 DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "")
+DEF_ATTRIB(SCALAR_LOAD, "Load is scalar", "", "")
 DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "")
 DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "")
 DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "")
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 9e5fcee1ee..01671d5451 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -333,6 +333,7 @@  static void mark_implicit_pred_writes(DisasContext *ctx)
 static void analyze_packet(DisasContext *ctx)
 {
     Packet *pkt = ctx->pkt;
+    ctx->need_pkt_has_store_s1 = false;
     for (int i = 0; i < pkt->num_insns; i++) {
         Insn *insn = &pkt->insn[i];
         ctx->insn = insn;
@@ -367,12 +368,15 @@  static void gen_start_packet(DisasContext *ctx)
     for (i = 0; i < STORES_MAX; i++) {
         ctx->store_width[i] = 0;
     }
-    tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1);
     ctx->s1_store_processed = false;
     ctx->pre_commit = true;
 
     analyze_packet(ctx);
 
+    if (ctx->need_pkt_has_store_s1) {
+        tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1);
+    }
+
     /*
      * pregs_written is used both in the analyze phase as well as the code
      * gen phase, so clear it again.
diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py
index 37c166dc0d..7e1f221b3c 100755
--- a/target/hexagon/gen_analyze_funcs.py
+++ b/target/hexagon/gen_analyze_funcs.py
@@ -200,6 +200,11 @@  def gen_analyze_func(f, tag, regs, imms):
         analyze_opn(f, tag, regtype, regid, toss, numregs, i)
         i += 1
 
+    has_generated_helper = (not hex_common.skip_qemu_helper(tag) and
+                            not hex_common.is_idef_parser_enabled(tag))
+    if (has_generated_helper and
+        'A_SCALAR_LOAD' in hex_common.attribdict[tag]):
+        f.write("    ctx->need_pkt_has_store_s1 = true;\n")
 
     f.write("}\n\n")
 
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index a29f61bb4f..76da362c11 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -89,6 +89,7 @@  def calculate_attribs():
     add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
     add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
     add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
+    add_qemu_macro_attrib('fLOAD', 'A_SCALAR_LOAD')
     add_qemu_macro_attrib('fSTORE', 'A_SCALAR_STORE')
 
     # Recurse down macros, find attributes from sub-macros