| Message ID | 20230308201925.258223-15-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | centralize CPU extensions logic | expand |
On 2023/3/9 4:19, Daniel Henrique Barboza wrote: > This restriction is found at the current implementation of write_misa() > in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while > also removing the checks we're doing considering that I or E can be > enabled. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 49f0fd2c11..7a5d202069 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1045,15 +1045,15 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu->cfg.ext_ifencei = true; > } > > - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > - error_setg(errp, > - "I and E extensions are incompatible"); > + /* We do not have RV32E support */ > + if (cpu->cfg.ext_e) { > + error_setg(errp, "E extension (RV32E) is not supported"); > return; > } > > - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > - error_setg(errp, > - "Either I or E extension must be set"); > + /* When RV32E is supported we'll need to check for either I or E */ > + if (!cpu->cfg.ext_i) { > + error_setg(errp, "I extension must be set"); We currently have supported the RV64E and RV32E in fact. Although we miss some checking when decoding, the current QEMU can run programs written for RVE. So we should not prohibit the RVE here. Zhiwei > return; > } >
On 3/9/23 04:10, LIU Zhiwei wrote: > > On 2023/3/9 4:19, Daniel Henrique Barboza wrote: >> This restriction is found at the current implementation of write_misa() >> in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while >> also removing the checks we're doing considering that I or E can be >> enabled. >> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> --- >> target/riscv/cpu.c | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 49f0fd2c11..7a5d202069 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -1045,15 +1045,15 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) >> cpu->cfg.ext_ifencei = true; >> } >> - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { >> - error_setg(errp, >> - "I and E extensions are incompatible"); >> + /* We do not have RV32E support */ >> + if (cpu->cfg.ext_e) { >> + error_setg(errp, "E extension (RV32E) is not supported"); >> return; >> } >> - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { >> - error_setg(errp, >> - "Either I or E extension must be set"); >> + /* When RV32E is supported we'll need to check for either I or E */ >> + if (!cpu->cfg.ext_i) { >> + error_setg(errp, "I extension must be set"); > > We currently have supported the RV64E and RV32E in fact. Although we miss some checking when decoding, the current QEMU can run programs written for RVE. So we should not prohibit the RVE here. Right, so I got fooled by write_misa() logic. I'll remove this patch. Thanks, Daniel > > Zhiwei > >> return; >> }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 49f0fd2c11..7a5d202069 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1045,15 +1045,15 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_ifencei = true; } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); + /* We do not have RV32E support */ + if (cpu->cfg.ext_e) { + error_setg(errp, "E extension (RV32E) is not supported"); return; } - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); + /* When RV32E is supported we'll need to check for either I or E */ + if (!cpu->cfg.ext_i) { + error_setg(errp, "I extension must be set"); return; }
This restriction is found at the current implementation of write_misa() in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while also removing the checks we're doing considering that I or E can be enabled. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)