Message ID | 20230314164948.539135-15-dbarboza@ventanamicro.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Tue, 14 Mar 2023 09:50:36 -0700 (PDT) From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PATCH for-8.1 v2 14/26] target/riscv: add RVG Date: Tue, 14 Mar 2023 13:49:36 -0300 Message-Id: <20230314164948.539135-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
target/riscv: rework CPU extensions validation
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expand
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 28d4c5f768..48ad7372b9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,6 +274,9 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) if (cfg->ext_j) { ext |= RVJ; } + if (cfg->ext_g) { + ext |= RVG; + } return ext; } @@ -293,6 +296,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, cfg->ext_u = misa_ext & RVU; cfg->ext_h = misa_ext & RVH; cfg->ext_j = misa_ext & RVJ; + cfg->ext_g = misa_ext & RVG; } static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2263629332..dbb4df9df0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,6 +82,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') /* Privileged specification version */
The 'G' bit in misa_ext is a virtual extension that enables a set of extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid setting it for write_misa(). Add it so we can gate write_misa() properly against it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+)