Message ID | 20230318200436.299464-11-dbarboza@ventanamicro.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Sat, 18 Mar 2023 13:05:10 -0700 (PDT) From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PATCH for-8.1 v3 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Date: Sat, 18 Mar 2023 17:04:20 -0300 Message-Id: <20230318200436.299464-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230318200436.299464-1-dbarboza@ventanamicro.com> References: <20230318200436.299464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
target/riscv: rework CPU extensions validation
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expand
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c7b6e7b84b..36c55abda0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -949,7 +949,8 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, doing a set_misa() in the end. + * cpu->cfg accordingly, setting env->misa_ext and + * misa_ext_mask in the end. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { @@ -1168,7 +1169,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) ext |= RVJ; } - set_misa(env, env->misa_mxl, ext); + env->misa_ext_mask = env->misa_ext = ext; } #ifndef CONFIG_USER_ONLY
set_misa() will be tuned up to do more than it's already doing and it will be redundant to what riscv_cpu_validate_set_extensions() does. Note that we don't ever change env->misa_mlx in this function, so set_misa() can be replaced by just assigning env->misa_ext and env->misa_ext_mask to 'ext'. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)