Message ID | 20230318200436.299464-2-dbarboza@ventanamicro.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | target/riscv: rework CPU extensions validation | expand |
On 2023/3/19 4:04, Daniel Henrique Barboza wrote: > The RVV verification will error out if fails and it's being done at the > end of riscv_cpu_validate_set_extensions(). Let's put it in its own > function and do it earlier. > > We'll move it out of riscv_cpu_validate_set_extensions() in the near future, > but for now this is enough to clean the code a bit. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 86 ++++++++++++++++++++++++++-------------------- > 1 file changed, 49 insertions(+), 37 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1e97473af2..18591aa53a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -802,6 +802,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > + Error **errp) > +{ > + int vext_version = VEXT_VERSION_1_00_0; > + > + if (!is_power_of_2(cfg->vlen)) { > + error_setg(errp, "Vector extension VLEN must be power of 2"); > + return; > + } > + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { > + error_setg(errp, > + "Vector extension implementation only supports VLEN " > + "in the range [128, %d]", RV_VLEN_MAX); > + return; > + } > + if (!is_power_of_2(cfg->elen)) { > + error_setg(errp, "Vector extension ELEN must be power of 2"); > + return; > + } > + if (cfg->elen > 64 || cfg->elen < 8) { > + error_setg(errp, > + "Vector extension implementation only supports ELEN " > + "in the range [8, 64]"); > + return; > + } > + if (cfg->vext_spec) { > + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { > + vext_version = VEXT_VERSION_1_00_0; > + } else { > + error_setg(errp, "Unsupported vector spec version '%s'", > + cfg->vext_spec); > + return; > + } > + } else { > + qemu_log("vector version is not specified, " > + "use the default value v1.0\n"); > + } > + set_vext_version(env, vext_version); > +} > + > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly, doing a set_misa() in the end. > @@ -809,6 +849,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > { > CPURISCVState *env = &cpu->env; > + Error *local_err = NULL; > uint32_t ext = 0; > > /* Do some ISA extension error checking */ > @@ -939,6 +980,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > } > } > > + if (cpu->cfg.ext_v) { > + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + } > + > if (cpu->cfg.ext_zk) { > cpu->cfg.ext_zkn = true; > cpu->cfg.ext_zkr = true; > @@ -993,44 +1042,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > ext |= RVH; > } > if (cpu->cfg.ext_v) { > - int vext_version = VEXT_VERSION_1_00_0; > ext |= RVV; > - if (!is_power_of_2(cpu->cfg.vlen)) { > - error_setg(errp, > - "Vector extension VLEN must be power of 2"); > - return; > - } > - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { > - error_setg(errp, > - "Vector extension implementation only supports VLEN " > - "in the range [128, %d]", RV_VLEN_MAX); > - return; > - } > - if (!is_power_of_2(cpu->cfg.elen)) { > - error_setg(errp, > - "Vector extension ELEN must be power of 2"); > - return; > - } > - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { > - error_setg(errp, > - "Vector extension implementation only supports ELEN " > - "in the range [8, 64]"); > - return; > - } > - if (cpu->cfg.vext_spec) { > - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { > - vext_version = VEXT_VERSION_1_00_0; > - } else { > - error_setg(errp, > - "Unsupported vector spec version '%s'", > - cpu->cfg.vext_spec); > - return; > - } > - } else { > - qemu_log("vector version is not specified, " > - "use the default value v1.0\n"); > - } > - set_vext_version(env, vext_version); Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > } > if (cpu->cfg.ext_j) { > ext |= RVJ;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..18591aa53a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -802,6 +802,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + int vext_version = VEXT_VERSION_1_00_0; + + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + vext_version = VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -809,6 +849,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env = &cpu->env; + Error *local_err = NULL; uint32_t ext = 0; /* Do some ISA extension error checking */ @@ -939,6 +980,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } + if (cpu->cfg.ext_v) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; @@ -993,44 +1042,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) ext |= RVH; } if (cpu->cfg.ext_v) { - int vext_version = VEXT_VERSION_1_00_0; ext |= RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version = VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); } if (cpu->cfg.ext_j) { ext |= RVJ;
The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(). Let's put it in its own function and do it earlier. We'll move it out of riscv_cpu_validate_set_extensions() in the near future, but for now this is enough to clean the code a bit. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 86 ++++++++++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 37 deletions(-)