| Message ID | 20230321180012.2545-2-Jonathan.Cameron@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/cxl: Fix decoder commit and uncommit handling | expand |
On Tue, Mar 21, 2023 at 06:00:11PM +0000, Jonathan Cameron wrote: > Not a real problem yet as all supported architectures are > little endian, but continue to tidy these up when touching > code for other reasons. > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Hi Jonathan, Did you forget to send the other patch in this series by any chance? Fan > --- > hw/cxl/cxl-component-utils.c | 10 ++++------ > hw/mem/cxl_type3.c | 9 ++++++--- > 2 files changed, 10 insertions(+), 9 deletions(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index b665d4f565..a3e6cf75cf 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -47,14 +47,12 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, > break; > } > > - memory_region_transaction_begin(); > - stl_le_p((uint8_t *)cache_mem + offset, value); > if (should_commit) { > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); > + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > } > - memory_region_transaction_commit(); > + stl_le_p((uint8_t *)cache_mem + offset, value); > } > > static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > index abe60b362c..846089ccda 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -314,14 +314,17 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) > { > ComponentRegisters *cregs = &ct3d->cxl_cstate.crb; > uint32_t *cache_mem = cregs->cache_mem_registers; > + uint32_t ctrl; > > assert(which == 0); > > + ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL); > /* TODO: Sanity checks that the decoder is possible */ > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); > + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0); > + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > + stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL, ctrl); > } > > static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err) > -- > 2.37.2 >
On Tue, 21 Mar 2023 19:28:02 +0000 Fan Ni <fan.ni@samsung.com> wrote: > On Tue, Mar 21, 2023 at 06:00:11PM +0000, Jonathan Cameron wrote: > > Not a real problem yet as all supported architectures are > > little endian, but continue to tidy these up when touching > > code for other reasons. > > > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > Hi Jonathan, > Did you forget to send the other patch in this series by any chance? No. All 3 emails went out, but not all seem to have made it to the lists. I have them via an internal reflector so maybe a Huawei network glitch. Odd. I'll try a resend. Thanks for pointing this out! Jonathan > > Fan > > --- > > hw/cxl/cxl-component-utils.c | 10 ++++------ > > hw/mem/cxl_type3.c | 9 ++++++--- > > 2 files changed, 10 insertions(+), 9 deletions(-) > > > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > > index b665d4f565..a3e6cf75cf 100644 > > --- a/hw/cxl/cxl-component-utils.c > > +++ b/hw/cxl/cxl-component-utils.c > > @@ -47,14 +47,12 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, > > break; > > } > > > > - memory_region_transaction_begin(); > > - stl_le_p((uint8_t *)cache_mem + offset, value); > > if (should_commit) { > > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); > > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > > + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > > + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); > > + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > > } > > - memory_region_transaction_commit(); > > + stl_le_p((uint8_t *)cache_mem + offset, value); > > } > > > > static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > > index abe60b362c..846089ccda 100644 > > --- a/hw/mem/cxl_type3.c > > +++ b/hw/mem/cxl_type3.c > > @@ -314,14 +314,17 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) > > { > > ComponentRegisters *cregs = &ct3d->cxl_cstate.crb; > > uint32_t *cache_mem = cregs->cache_mem_registers; > > + uint32_t ctrl; > > > > assert(which == 0); > > > > + ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL); > > /* TODO: Sanity checks that the decoder is possible */ > > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); > > + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMIT, 0); > > + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0); > > + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > > > > - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); > > + stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL, ctrl); > > } > > > > static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err) > > -- > > 2.37.2 > >
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index b665d4f565..a3e6cf75cf 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -47,14 +47,12 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset, break; } - memory_region_transaction_begin(); - stl_le_p((uint8_t *)cache_mem + offset, value); if (should_commit) { - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMIT, 0); + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); + value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); } - memory_region_transaction_commit(); + stl_le_p((uint8_t *)cache_mem + offset, value); } static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value, diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index abe60b362c..846089ccda 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -314,14 +314,17 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) { ComponentRegisters *cregs = &ct3d->cxl_cstate.crb; uint32_t *cache_mem = cregs->cache_mem_registers; + uint32_t ctrl; assert(which == 0); + ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL); /* TODO: Sanity checks that the decoder is possible */ - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMIT, 0); + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0); + ctrl = FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); - ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); + stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL, ctrl); } static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err)
Not a real problem yet as all supported architectures are little endian, but continue to tidy these up when touching code for other reasons. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/cxl/cxl-component-utils.c | 10 ++++------ hw/mem/cxl_type3.c | 9 ++++++--- 2 files changed, 10 insertions(+), 9 deletions(-)