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Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Sriram Yagnaraman Subject: [PATCH v8 3/8] igb: add ICR_RXDW Date: Wed, 22 Mar 2023 10:26:59 +0100 Message-Id: <20230322092704.22776-4-sriram.yagnaraman@est.tech> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230322092704.22776-1-sriram.yagnaraman@est.tech> References: <20230322092704.22776-1-sriram.yagnaraman@est.tech> X-ClientProxiedBy: OS6P279CA0141.NORP279.PROD.OUTLOOK.COM (2603:10a6:e10:3a::17) To DBBP189MB1433.EURP189.PROD.OUTLOOK.COM (2603:10a6:10:1e7::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DBBP189MB1433:EE_|DU0P189MB2201:EE_ X-MS-Office365-Filtering-Correlation-Id: 44979a83-4181-4dbc-b758-08db2ab79da9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yuPx9L32mZG+PDnrMG4AmXz0RbdSjumBF2EDAvtz5VSmQKrdPAq5ah5TaWp8jXOgtVD7W/UAXXquggYkWIB4kqr8Gm1HSsLBwgbFKX/OXRJBIw/nGZRyczDnossFfpewneWtEQdRyaYqUTuR/E8bNj/RPFiFTzYt9OjhfAF07jaC9mSL6IOcPMBueNrHfR9Z1KHbg4Rp2H/7/BXj2DEK1Op+x/dywWHUswRD2Bopy0IGCr6QsTupsrNmzb54RuFi1/vm4GYDEzdWSitAqrCggvRpPdDsC9jnhRabHg9RiehPOBVIZ3rbkCX/o02AdgFgO4BcbA+SuVGuf2AQbzEEI5XJt8NlaATmF5zA1v4hnfVuALzRpAhs/YWARxqL3khlA0AmgRG+8w38cNLmS5ZSiSlLMqfrnsRow2nSNE1f2Zxw3hkyWNwQEQODfcpXoQZo4JylcBPQP0g3/hMyXEFWojp0zs+NulDuEWe2RBt1ToK794OBgKqt8ZXQHC6tgaCqhktlXvQromvPhX+LwiC0vaZQcErC99yzgTLPQbw0YKqWmRyMHr93Xt0IGLkcCsnhrlVtTa0Q04a1pqXaYuG5afwuGQtw7TJ7yLGKGJ2oYy5X5FLbWwVOa3JO8pvwejuglk7W9wrPb7BobCBBhKPcTJ0qj4fxEuTljP7aB8+7h8nhoiyaU5z803tyNYkLY5wHI5LcRpManpyNKf6HzvJRoZO/+mSvUcFHs/ig9JbDZxw= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=sriram.yagnaraman@est.tech; helo=EUR03-DBA-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IGB uses RXDW ICR bit to indicate that rx descriptor has been written back. This is the same as RXT0 bit in older HW. Signed-off-by: Sriram Yagnaraman --- hw/net/e1000x_regs.h | 4 ++++ hw/net/igb_core.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h index c0832fa23d..6d3c4c6d3a 100644 --- a/hw/net/e1000x_regs.h +++ b/hw/net/e1000x_regs.h @@ -335,6 +335,7 @@ #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ #define E1000_ICR_RXO 0x00000040 /* rx overrun */ #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_RXDW 0x00000080 /* rx desc written back */ #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ @@ -378,6 +379,7 @@ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -407,6 +409,7 @@ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -441,6 +444,7 @@ #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index fe6c7518e9..c575d4a615 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -1580,7 +1580,7 @@ igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, continue; } - n |= E1000_ICR_RXT0; + n |= E1000_ICR_RXDW; igb_rx_fix_l4_csum(core, core->rx_pkt); igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);